>Date: Fri, 29 Dec 1995 09:14:53 +1100
>From: George Michaelson <ggm@connect.com.au>

>had to disable my onboard cache to get NetBSD to run.
>its a MP5-TRI from PCPartner. triton chipset.
>
>I have jumper options to control:
>
>	L1 cache protocol (write back (default) or write through)

Try setting this one to write-through, and see if that helps.
Write-back caching will fail in the presence of bus masters other than
the CPU unless the motherboard has implemented cache coherency
properly.  Cache coherency protocols are nontrivial, so they may have
done it wrongly.

>	L2 cache size (0,256,512 (selected)

Make sure this matches the amount of cache SRAM you have installed;
but if this setting is incorrect, I don't see how anything would
work.

>Is there a lucid description of whats going on here online anywhere?

Take a University course on high-performance computer architecture.
I can provide some book titles on the subject, if such are desired.

>compile options to get cache used properly?

There are options for Cyrix 486DLC motherboards, but they won't help
you--you have a Pentium.

>(behavior was crash on panic during system startup)

Did the kernel print any messages?
-- 
Mike Long <mike.long@analog.com>           http://www.shore.net/~mikel
VLSI Design Engineer         finger mikel@shore.net for PGP public key
Analog Devices, CPD Division          CCBF225E7D3F7ECB2C8F7ABB15D9BE7B
Norwood, MA 02062 USA       (eq (opinion 'ADI) (opinion 'mike)) -> nil