Re: libcrypto: Illegal instruction ``pshufb'' on non-sse3 CPU

[Timo Buhrmester <fstd.lkml%gmail.com@localhost>]

Joerg:

> > [...] SIGILL [...] due to using the ``pshufb'' instruction
> I think you are actually ending up in the AVX code path. The question is
> why. What is the value OPENSSL_ia32cap_P?
That's 0x78bffff



Masanobu:

>  For x86, /proc/cpuinfo have not maintained for many years...
> To avoid this problem, use "cpuctl identify 0" instead of /proc/cpuinfo
> to check cpu features (PR#49246).
# cpuctl identify 0
cpu0: highest basic info 00000005
cpu0: highest extended info 8000001b
cpu0: "AMD Athlon(tm) II X2 265 Processor"
cpu0: AMD Family 10h (686-class), 3311.46 MHz
cpu0: family 0x10 model 0x6 stepping 0x3 (id 0x100f63)
cpu0: features 0x178bfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE>
cpu0: features 0x178bfbff<MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT>
cpu0: features1 0x802009<SSE3,MONITOR,CX16,POPCNT>
cpu0: features2 0xefd3fbff<SYSCALL/SYSRET,NOX,MMXX,FFXSR,P1GB,RDTSCP,LONG>
cpu0: features2 0xefd3fbff<3DNOW2,3DNOW>
cpu0: features3 0x37ff<LAHF,CMPLEGACY,SVM,EAPIC,ALTMOVCR0,LZCNT,SSE4A>
cpu0: features3 0x37ff<MISALIGNSSE,3DNOWPREFETCH,OSVW,IBS,SKINIT,WDT>
cpu0: I-cache 64KB 64B/line 2-way, D-cache 64KB 64B/line 2-way
cpu0: L2 cache 1MB 64B/line 16-way
cpu0: ITLB 32 4KB entries fully associative, 16 2MB entries fully associative
cpu0: DTLB 48 4KB entries fully associative, 48 2MB entries fully associative
cpu0: L2 ITLB 512 4KB entries 4-way
cpu0: L2 DTLB 512 4KB entries 4-way, 128 2MB entries 2-way
cpu0: L1 1GB page DTLB 48 1GB entries fully associative
cpu0: L2 1GB page DTLB 16 1GB entries 8-way
cpu0: Initial APIC ID 0
cpu0: AMD Power Management features: 0x1f9<TS,TTP,HTC,STC,100,HWP,TSC>
cpu0: SVM Rev. 1
cpu0: SVM NASID 64
cpu0: SVM features 0xf<NP,LbrVirt,SVML,NRIPS>
cpu0: UCode version: 0x10000c8


Thanks for caring!
Kind regards