Re: tester need: MII PHY register read/write API change

[Masanobu SAITOH <msaitoh%execsw.org@localhost>]

On 2019/01/24 23:47, Riccardo Mottola wrote:
> Hello Masanobu,
>
> I updated and recompiled kernel,
>
> [     1.049407] re0 at pci5 dev 0 function 0: RealTek 8100E/8101E/8102E/8102EL PCIe 10/100BaseTX (rev. 0x02)
> [     1.049407] re0: interrupting at msix1 vec 0
> [     1.049407] re0: Ethernet address 64:31:50:7b:8f:55
> [     1.049407] re0: using 256 tx descriptors
> [     1.049407] rlphy0 at re0 phy 7: RTL8201L 10/100 media interface, rev. 1
>
> it would be re+rlphy I suppose, not listed in your list?

Yes, the combination is not listed, but MAC and PHY combination
is not important. re (re+rgephy) and rlphy(rtk+rlphy) are listed.

> Just want to confirm that it compiled and that it works fine.

 Anyway, thank you for your report!

> Thank you,
> Riccardo


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-----------------------------------------------
                SAITOH Masanobu (msaitoh%execsw.org@localhost
                                 msaitoh%netbsd.org@localhost)