[pkgsrc/trunk]: pkgsrc/cad/verilator Update to 4.012

[ryoon <ryoon%pkgsrc.org@localhost>]

details:   https://anonhg.NetBSD.org/pkgsrc/rev/f6cb7130f26c
branches:  trunk
changeset: 332014:f6cb7130f26c
user:      ryoon <ryoon%pkgsrc.org@localhost>
date:      Mon Apr 01 12:22:53 2019 +0000

description:
Update to 4.012

* flex from NetBSD base causes build failure, so use pkgsrc/devel/flex instead.

Changelog:
* Verilator 4.012 2019-3-23

***   Add +verilator+seed, bug1396. [Stan Sokorac]

***   Support $fread.  [Leendert van Doorn]

***   Support void' cast on functions called as tasks, bug1383. [Al Grant]

***   Add IGNOREDRETURN warning, bug1383.

****  Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland]

****  Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin]

****  Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen]

****  Fix MSVC compile error, bug1406. [Benjamin Gartner]

****  Fix maintainer test when no Parallel::Forker, msg2630. [Enzo Chi]

****  Fix +1364-1995ext flags applying too late, bug1384. [Al Grant]


* Verilator 4.010 2019-01-27

***   Removed --trace-lxt2, use --trace-fst instead.

****  For --xml, add additional information, bug1372. [Jonathan Kimmitt]

****  Add circular typedef error, bug1388.  [Al Grant]

****  Add unsupported for loops error, msg2692. [Yu Sheng Lin]

****  Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]

****  Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]

****  Fix error when no modules in $unit, bug1381. [Al Grant]

****  Fix missing too many digits warning, bug1380. [Jonathan Kimmitt]

****  Fix uninitialized data in verFiles and unroller, bug1385. bug1386. [Al Grant]

****  Fix internal error on xrefs into unrolled functions, bug1387. [Al Grant]

****  Fix DPI export void compiler error, bug1391. [Stan Sokorac]


* Verilator 4.008 2018-12-01

***   Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo]

***   In --xml-only show the original unmodified names, and add module_files
      and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere]

****  Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst]

****  Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton]

****  Add IMPORTSTAR warning on import::* inside $unit scope.

****  Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]

****  Fix hang on bad pattern keys, bug1364. [Matt Myers]

****  Fix crash due to cygwin bug in getline, bug1349. [Affe Mao]

****  Fix __Slow files getting compiled with OPT_FAST, bug1370. [Thomas Watts]

diffstat:

 cad/verilator/Makefile |   6 ++++--
 cad/verilator/PLIST    |   6 +-----
 cad/verilator/distinfo |  10 +++++-----
 3 files changed, 10 insertions(+), 12 deletions(-)

diffs (64 lines):

diff -r f49102fec150 -r f6cb7130f26c cad/verilator/Makefile
--- a/cad/verilator/Makefile    Mon Apr 01 12:16:53 2019 +0000
+++ b/cad/verilator/Makefile    Mon Apr 01 12:22:53 2019 +0000
@@ -1,6 +1,6 @@
-# $NetBSD: Makefile,v 1.1 2018/12/16 09:05:12 ryoon Exp $
+# $NetBSD: Makefile,v 1.2 2019/04/01 12:22:53 ryoon Exp $
 
-DISTNAME=      verilator-4.006
+DISTNAME=      verilator-4.012
 CATEGORIES=    cad
 MASTER_SITES=  https://www.veripool.org/ftp/
 EXTRACT_SUFX=  .tgz
@@ -15,6 +15,8 @@
 USE_TOOLS+=    bison flex gmake perl pkg-config
 USE_LANGUAGES= c c++
 
+TOOLS_PLATFORM.flex=   # Use flex from pkgsrc
+
 REPLACE_PERL+= test_regress/*.pl
 REPLACE_PERL+= test_regress/t/*.pl
 
diff -r f49102fec150 -r f6cb7130f26c cad/verilator/PLIST
--- a/cad/verilator/PLIST       Mon Apr 01 12:16:53 2019 +0000
+++ b/cad/verilator/PLIST       Mon Apr 01 12:22:53 2019 +0000
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.1 2018/12/16 09:05:12 ryoon Exp $
+@comment $NetBSD: PLIST,v 1.2 2019/04/01 12:22:53 ryoon Exp $
 bin/verilator
 bin/verilator_bin
 bin/verilator_bin_dbg
@@ -35,8 +35,6 @@
 share/verilator/include/gtkwave/fst_config.h
 share/verilator/include/gtkwave/fstapi.c
 share/verilator/include/gtkwave/fstapi.h
-share/verilator/include/gtkwave/lxt2_write.cpp
-share/verilator/include/gtkwave/lxt2_write.h
 share/verilator/include/gtkwave/lz4.c
 share/verilator/include/gtkwave/lz4.h
 share/verilator/include/gtkwave/wavealloca.h
@@ -55,8 +53,6 @@
 share/verilator/include/verilated_fst_c.h
 share/verilator/include/verilated_heavy.h
 share/verilator/include/verilated_imp.h
-share/verilator/include/verilated_lxt2_c.cpp
-share/verilator/include/verilated_lxt2_c.h
 share/verilator/include/verilated_save.cpp
 share/verilator/include/verilated_save.h
 share/verilator/include/verilated_sc.h
diff -r f49102fec150 -r f6cb7130f26c cad/verilator/distinfo
--- a/cad/verilator/distinfo    Mon Apr 01 12:16:53 2019 +0000
+++ b/cad/verilator/distinfo    Mon Apr 01 12:22:53 2019 +0000
@@ -1,7 +1,7 @@
-$NetBSD: distinfo,v 1.1 2018/12/16 09:05:12 ryoon Exp $
+$NetBSD: distinfo,v 1.2 2019/04/01 12:22:53 ryoon Exp $
 
-SHA1 (verilator-4.006.tgz) = f731c8c8b4b366d806e6a80a52d0b23a5528a054
-RMD160 (verilator-4.006.tgz) = 541a370ceb99a012837ced786bff104510533101
-SHA512 (verilator-4.006.tgz) = f3383b078c22ad8d487fac08ac44b107b7c77a643ced1c6f6e3d03600b696de1d0dabb921b086bca145f361b011d8a3d529f9317a2ccd6a2ec3755067d1cb3e5
-Size (verilator-4.006.tgz) = 2510084 bytes
+SHA1 (verilator-4.012.tgz) = 653688c0dc8521d8d3ab9f9e94180f2271ec08ff
+RMD160 (verilator-4.012.tgz) = d15a54b8243caf5e22c3f9c6f6ff76ee7a37219b
+SHA512 (verilator-4.012.tgz) = b2ebe685e5801eb25e76cc9820def7586324b4854651756e0df4c4e21b218ebc2bafd3ef8157d22d90cf6f940089d6d4ac9981e26abf602a5b47f58d878c05ea
+Size (verilator-4.012.tgz) = 2513309 bytes
 SHA1 (patch-Makefile.in) = 3c91715cdfaba04120ada7a328b46e0571767e06