pkgsrc-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[pkgsrc/trunk]: pkgsrc/graphics/MesaLib/patches Assume that whatever problems...
details: https://anonhg.NetBSD.org/pkgsrc/rev/10f2c4c861aa
branches: trunk
changeset: 650640:10f2c4c861aa
user: tnn <tnn%pkgsrc.org@localhost>
date: Sat Apr 25 11:13:23 2015 +0000
description:
Assume that whatever problems this patch set fixed are fixed upstream in
Mesa 10.5.3. There are no patch comments or CVS history for these and
the original author couldn't provide details.
diffstat:
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__batchbuffer.c | 16 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__tris.c | 13 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw.c | 22 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw__upload.c | 19 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__misc__state.c | 142 ----------
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__vs__state.c | 17 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__wm__state.c | 38 --
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_intel__batchbuffer.c | 16 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_intel_intel__context.c | 13 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_intel_intel__context.h | 27 -
graphics/MesaLib/patches/patch-src_mesa_drivers_dri_mach64_mach64__context.h | 23 -
11 files changed, 0 insertions(+), 346 deletions(-)
diffs (truncated from 390 to 300 lines):
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__batchbuffer.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__batchbuffer.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,16 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i915_intel__batchbuffer.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i915/intel_batchbuffer.c.orig 2011-10-15 04:29:59.000000000 +0000
-+++ src/mesa/drivers/dri/i915/intel_batchbuffer.c
-@@ -427,8 +427,10 @@ intel_batchbuffer_emit_mi_flush(struct i
- OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
- PIPE_CONTROL_WRITE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-+ PIPE_CONTROL_VF_CACHE_INVALIDATE |
- PIPE_CONTROL_TC_FLUSH |
-- PIPE_CONTROL_NO_WRITE);
-+ PIPE_CONTROL_NO_WRITE |
-+ PIPE_CONTROL_CS_STALL);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
- ADVANCE_BATCH();
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__tris.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i915_intel__tris.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i915_intel__tris.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i915/intel_tris.c.orig 2011-10-15 00:43:58.000000000 +0000
-+++ src/mesa/drivers/dri/i915/intel_tris.c
-@@ -337,7 +337,7 @@ void intel_finish_vb(struct intel_contex
- * Emit primitives as inline vertices *
- ***********************************************************************/
-
--#ifdef __i386__
-+#if (defined(i386) || defined(__i386__)) && !(defined(__SOLARIS__) || defined(sun))
- #define COPY_DWORDS( j, vb, vertsize, v ) \
- do { \
- int __tmp; \
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_brw__draw.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i965/brw_draw.c.orig 2013-04-23 05:46:06.246377394 +0000
-+++ src/mesa/drivers/dri/i965/brw_draw.c
-@@ -168,7 +168,7 @@ static void brw_emit_prim(struct brw_con
- * and missed flushes of the render cache as it heads to other parts of
- * the besides the draw code.
- */
-- if (intel->always_flush_cache) {
-+ if ((intel->always_flush_cache) || (intel->gen == 6)) {
- intel_batchbuffer_emit_mi_flush(intel);
- }
-
-@@ -185,7 +185,7 @@ static void brw_emit_prim(struct brw_con
-
- intel->batch.need_workaround_flush = true;
-
-- if (intel->always_flush_cache) {
-+ if ((intel->always_flush_cache) || (intel->gen == 6)) {
- intel_batchbuffer_emit_mi_flush(intel);
- }
- }
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw__upload.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__draw__upload.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,19 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_brw__draw__upload.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i965/brw_draw_upload.c.orig 2011-10-15 00:43:58.000000000 +0000
-+++ src/mesa/drivers/dri/i965/brw_draw_upload.c
-@@ -531,8 +531,14 @@ static void brw_emit_vertices(struct brw
- struct intel_context *intel = intel_context(ctx);
- GLuint i;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < (13 + 4*brw->vb.nr_buffers + 2* brw->vb.nr_enabled)*4)
-+ intel_batchbuffer_flush(intel);
-+ }
- brw_emit_query_begin(brw);
-
-+
- /* If the VS doesn't read any inputs (calculating vertex position from
- * a state variable for some reason, for example), emit a single pad
- * VERTEX_ELEMENT struct and bail.
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__misc__state.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_brw__misc__state.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_brw__misc__state.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i965/brw_misc_state.c.orig 2013-04-23 05:46:06.246006959 +0000
-+++ src/mesa/drivers/dri/i965/brw_misc_state.c
-@@ -223,6 +223,12 @@ static void emit_depthbuffer(struct brw_
- struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
- unsigned int len;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 31*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
- * non-pipelined state that will need the PIPE_CONTROL workaround.
- */
-@@ -456,6 +462,12 @@ static void upload_polygon_stipple(struc
- if (!ctx->Polygon.StippleFlag)
- return;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 41*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- if (intel->gen == 6)
- intel_emit_post_sync_nonzero_flush(intel);
-
-@@ -504,6 +516,12 @@ static void upload_polygon_stipple_offse
- if (!ctx->Polygon.StippleFlag)
- return;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 10*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- if (intel->gen == 6)
- intel_emit_post_sync_nonzero_flush(intel);
-
-@@ -548,6 +566,12 @@ static void upload_aa_line_parameters(st
- if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
- return;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 11*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- if (intel->gen == 6)
- intel_emit_post_sync_nonzero_flush(intel);
-
-@@ -581,6 +605,12 @@ static void upload_line_stipple(struct b
- if (!ctx->Line.StippleFlag)
- return;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 11*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- if (intel->gen == 6)
- intel_emit_post_sync_nonzero_flush(intel);
-
-@@ -612,8 +642,62 @@ static void upload_invarient_state( stru
- struct intel_context *intel = &brw->intel;
-
- /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
-- if (intel->gen == 6)
-- intel_emit_post_sync_nonzero_flush(intel);
-+ if (intel->gen == 6) {
-+ int i;
-+
-+ if (intel->batch.need_workaround_flush) {
-+
-+ BEGIN_BATCH(33);
-+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
-+ OUT_BATCH(PIPE_CONTROL_CS_STALL |
-+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
-+ OUT_BATCH(0); /* address */
-+ OUT_BATCH(0); /* write data */
-+
-+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
-+ OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-+ OUT_RELOC(intel->batch.workaround_bo,
-+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
-+ OUT_BATCH(0); /* write data */
-+ } else
-+ BEGIN_BATCH(25);
-+ /* Select the 3D pipeline (as opposed to media) */
-+ OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
-+
-+ OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (1));
-+ OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
-+ MS_NUMSAMPLES_1);
-+ OUT_BATCH(0); /* positions for 4/8-sample */
-+
-+ OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
-+ OUT_BATCH(1);
-+
-+ if (intel->gen < 7) {
-+ for (i = 0; i < 4; i++) {
-+ OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
-+ OUT_BATCH(i << SVB_INDEX_SHIFT);
-+ OUT_BATCH(0);
-+ OUT_BATCH(0xffffffff);
-+ }
-+ }
-+
-+ /* 0x61020000 State Instruction Pointer */
-+ {
-+ OUT_BATCH(CMD_STATE_INSN_POINTER);
-+ OUT_BATCH(0);
-+ }
-+
-+
-+ {
-+ OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
-+ (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
-+ }
-+ ADVANCE_BATCH();
-+
-+ if (intel->batch.need_workaround_flush)
-+ intel->batch.need_workaround_flush = false;
-+
-+ } else {
-
- {
- /* 0x61040000 Pipeline Select */
-@@ -693,6 +777,7 @@ static void upload_invarient_state( stru
-
- BRW_BATCH_STRUCT(brw, &vfs);
- }
-+ }
- }
-
- const struct brw_tracked_state brw_invarient_state = {
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__vs__state.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__vs__state.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,17 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_gen6__vs__state.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i965/gen6_vs_state.c.orig 2011-11-23 01:09:52.000000000 +0000
-+++ src/mesa/drivers/dri/i965/gen6_vs_state.c
-@@ -120,6 +120,12 @@ upload_vs_state(struct brw_context *brw)
- {
- struct intel_context *intel = &brw->intel;
-
-+ /* workaround for gen6, reserve enough space for HW workaround */
-+ if (intel->gen == 6) {
-+ if (intel_batchbuffer_space(intel) < 23*4)
-+ intel_batchbuffer_flush(intel);
-+ }
-+
- if (brw->vs.push_const_size == 0) {
- /* Disable the push constant buffers. */
- BEGIN_BATCH(5);
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__wm__state.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_gen6__wm__state.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_gen6__wm__state.c,v 1.1 2013/05/16 05:22:02 richard Exp $
-
---- src/mesa/drivers/dri/i965/gen6_wm_state.c.orig 2011-10-15 00:43:58.000000000 +0000
-+++ src/mesa/drivers/dri/i965/gen6_wm_state.c
-@@ -102,15 +102,14 @@ upload_wm_state(struct brw_context *brw)
- /* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_params == 0) {
- /* Disable the push constant buffers. */
-- BEGIN_BATCH(5);
-+ BEGIN_BATCH(14);
- OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-- ADVANCE_BATCH();
- } else {
-- BEGIN_BATCH(5);
-+ BEGIN_BATCH(14);
- OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
- GEN6_CONSTANT_BUFFER_0_ENABLE |
- (5 - 2));
-@@ -123,7 +122,6 @@ upload_wm_state(struct brw_context *brw)
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-- ADVANCE_BATCH();
- }
-
- dw2 = dw4 = dw5 = dw6 = 0;
-@@ -183,7 +181,6 @@ upload_wm_state(struct brw_context *brw)
- dw6 |= brw_count_bits(brw->fragment_program->Base.InputsRead) <<
- GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
-
-- BEGIN_BATCH(9);
- OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
- OUT_BATCH(brw->wm.prog_offset);
- OUT_BATCH(dw2);
diff -r 403420002a7d -r 10f2c4c861aa graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_intel__batchbuffer.c
--- a/graphics/MesaLib/patches/patch-src_mesa_drivers_dri_i965_intel__batchbuffer.c Sat Apr 25 10:45:13 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,16 +0,0 @@
-$NetBSD: patch-src_mesa_drivers_dri_i965_intel__batchbuffer.c,v 1.1 2013/05/16 05:22:02 richard Exp $
Home |
Main Index |
Thread Index |
Old Index