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CVS commit: pkgsrc/cad/MyHDL-iverilog



Module Name:    pkgsrc
Committed By:   drochner
Date:           Wed Apr  1 17:26:07 UTC 2009

Modified Files:
        pkgsrc/cad/MyHDL-iverilog: Makefile

Log Message:
this needs verilog-current to build


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 pkgsrc/cad/MyHDL-iverilog/Makefile

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



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