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CVS commit: pkgsrc/cad



Module Name:    pkgsrc
Committed By:   kamil
Date:           Sun Oct  9 13:15:03 UTC 2016

Modified Files:
        pkgsrc/cad: Makefile

Log Message:
Add cad/veriwell


To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.91 pkgsrc/cad/Makefile

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/cad/Makefile
diff -u pkgsrc/cad/Makefile:1.90 pkgsrc/cad/Makefile:1.91
--- pkgsrc/cad/Makefile:1.90    Sat Oct  8 23:07:02 2016
+++ pkgsrc/cad/Makefile Sun Oct  9 13:15:03 2016
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.90 2016/10/08 23:07:02 kamil Exp $
+# $NetBSD: Makefile,v 1.91 2016/10/09 13:15:03 kamil Exp $
 #
 
 COMMENT=       CAD tools
@@ -64,6 +64,7 @@ SUBDIR+=      tnt-mmtl
 SUBDIR+=       transcalc
 SUBDIR+=       verilog
 SUBDIR+=       verilog-mode
+SUBDIR+=       veriwell
 SUBDIR+=       vipec
 SUBDIR+=       wcalc
 SUBDIR+=       wcalc-docs



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