CVS commit: pkgsrc/cad/py-MyHDL

To: pkgsrc-changes%NetBSD.org@localhost
Subject: CVS commit: pkgsrc/cad/py-MyHDL
From: "Makoto Fujiwara" <mef%netbsd.org@localhost>
Date: Thu, 12 Apr 2018 15:08:58 +0000

Module Name:    pkgsrc
Committed By:   mef
Date:           Thu Apr 12 15:08:58 UTC 2018

Modified Files:
        pkgsrc/cad/py-MyHDL: Makefile.common PLIST distinfo

Log Message:
Update cad/MyHDL from 0.9.0 to 0.10

pkgsrc packages altered:
 - cad/MyHDL-gplcver
 - cad/MyHDL-iverilog
 - cad/py-MyHDL

upstream changelog
------------------------
What’s new in MyHDL 0.10

The block decorator

Rationale

The historical approach for hierarchy extraction in MyHDL suffers from
significant issues. This results in complex code, a number of non-intuitive API
concepts, and difficulties for future development.

In this release, a new block decorator is introduced to address these issues.

For an in-depth discussion, see mep-114.

API

block() :noindex:

    The block decorator enables a method-based API which is more consistent,
    simplifies implementation, and reduces the size of the myhdl namespace.

    The methods work on block instances, created by calling a function
    decorated with the block decorator:

    @block
    def myblock(<ports>):
    ...
    return <instances>

    inst = myblock(<port-associations>)
    # inst supports the methods of the block instance API

The API on a block instance looks as follows:

<block_instance>.run_sim(duration=None)

    Run a simulation “forever” (default) or for a specified duration.

<block_instance>.config_sim(backend='myhdl', trace=False)

    - Optional simulation configuration:
    - backend: Defaults to ‘myhdl
    - trace: Enable waveform tracing, default False.

<block_instance>.quit_sim()

    Quit an active simulation. This is method is currently required because
    only a single simulation can be active.

<block_instance>.convert(hdl='Verilog', **kwargs)

    - Converts MyHDL code to a target HDL.
    - hdl: ‘VHDL’ or ‘Verilog’. Defaults to Verilog.
    - Supported keyword arguments:
    - path: Destination folder. Defaults to current working dir.
    - name: Module and output file name. Defaults to self.mod.__name__.
    - trace: Whether the testbench should dump all signal waveforms. Defaults to
      False.
    - testbench: Verilog only. Specifies whether a testbench should be created.
      Defaults to True.
    - timescale: timescale parameter. Defaults to ‘1ns/10ps’. Verilog only.

<block_instance>.verify_convert()

    Verify conversion output, by comparing target HDL simulation log with MyHDL
    simulation log.

<block_instance>.analyze_convert()

    Analyze conversion output by compilation with target HDL compiler.

Backwards compatibility issues

In the 0.10 release, the old API still available next to the new API based on
the block decorator.

It is likely that the old API will be deprecated in a future release, resulting
in backwards incompatibility for legacy code. Therefore, users are encouraged
to start using the new API in their development methodology.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 pkgsrc/cad/py-MyHDL/Makefile.common
cvs rdiff -u -r1.10 -r1.11 pkgsrc/cad/py-MyHDL/PLIST
cvs rdiff -u -r1.9 -r1.10 pkgsrc/cad/py-MyHDL/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/cad/py-MyHDL/Makefile.common
diff -u pkgsrc/cad/py-MyHDL/Makefile.common:1.1 pkgsrc/cad/py-MyHDL/Makefile.common:1.2
--- pkgsrc/cad/py-MyHDL/Makefile.common:1.1     Sun Oct  9 03:15:57 2016
+++ pkgsrc/cad/py-MyHDL/Makefile.common Thu Apr 12 15:08:58 2018
@@ -1,10 +1,10 @@
-# $NetBSD: Makefile.common,v 1.1 2016/10/09 03:15:57 kamil Exp $
+# $NetBSD: Makefile.common,v 1.2 2018/04/12 15:08:58 mef Exp $
 #
 # used by cad/MyHDL-gplcver/Makefile
 # used by cad/MyHDL-iverilog/Makefile
 
 GITHUB_PROJECT=        myhdl
-DISTNAME=      myhdl-0.9.0
+DISTNAME=      myhdl-0.10
 CATEGORIES=    cad python
 MASTER_SITES=  ${MASTER_SITE_GITHUB:=jandecaluwe/}
 

Index: pkgsrc/cad/py-MyHDL/PLIST
diff -u pkgsrc/cad/py-MyHDL/PLIST:1.10 pkgsrc/cad/py-MyHDL/PLIST:1.11
--- pkgsrc/cad/py-MyHDL/PLIST:1.10      Sun Oct  9 03:15:57 2016
+++ pkgsrc/cad/py-MyHDL/PLIST   Thu Apr 12 15:08:58 2018
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.10 2016/10/09 03:15:57 kamil Exp $
+@comment $NetBSD: PLIST,v 1.11 2018/04/12 15:08:58 mef Exp $
 ${PYSITELIB}/${EGG_FILE}/PKG-INFO
 ${PYSITELIB}/${EGG_FILE}/SOURCES.txt
 ${PYSITELIB}/${EGG_FILE}/dependency_links.txt
@@ -33,9 +33,9 @@ ${PYSITELIB}/myhdl/_always_seq.pyo
 ${PYSITELIB}/myhdl/_bin.py
 ${PYSITELIB}/myhdl/_bin.pyc
 ${PYSITELIB}/myhdl/_bin.pyo
-${PYSITELIB}/myhdl/_cell_deref.py
-${PYSITELIB}/myhdl/_cell_deref.pyc
-${PYSITELIB}/myhdl/_cell_deref.pyo
+${PYSITELIB}/myhdl/_block.py
+${PYSITELIB}/myhdl/_block.pyc
+${PYSITELIB}/myhdl/_block.pyo
 ${PYSITELIB}/myhdl/_compat.py
 ${PYSITELIB}/myhdl/_compat.pyc
 ${PYSITELIB}/myhdl/_compat.pyo
@@ -51,6 +51,12 @@ ${PYSITELIB}/myhdl/_enum.pyo
 ${PYSITELIB}/myhdl/_extractHierarchy.py
 ${PYSITELIB}/myhdl/_extractHierarchy.pyc
 ${PYSITELIB}/myhdl/_extractHierarchy.pyo
+${PYSITELIB}/myhdl/_getHierarchy.py
+${PYSITELIB}/myhdl/_getHierarchy.pyc
+${PYSITELIB}/myhdl/_getHierarchy.pyo
+${PYSITELIB}/myhdl/_getcellvars.py
+${PYSITELIB}/myhdl/_getcellvars.pyc
+${PYSITELIB}/myhdl/_getcellvars.pyo
 ${PYSITELIB}/myhdl/_instance.py
 ${PYSITELIB}/myhdl/_instance.pyc
 ${PYSITELIB}/myhdl/_instance.pyo
@@ -81,6 +87,12 @@ ${PYSITELIB}/myhdl/_tristate.pyo
 ${PYSITELIB}/myhdl/_util.py
 ${PYSITELIB}/myhdl/_util.pyc
 ${PYSITELIB}/myhdl/_util.pyo
+${PYSITELIB}/myhdl/_visitors.py
+${PYSITELIB}/myhdl/_visitors.pyc
+${PYSITELIB}/myhdl/_visitors.pyo
+${PYSITELIB}/myhdl/conversion/_VHDLNameValidation.py
+${PYSITELIB}/myhdl/conversion/_VHDLNameValidation.pyc
+${PYSITELIB}/myhdl/conversion/_VHDLNameValidation.pyo
 ${PYSITELIB}/myhdl/conversion/__init__.py
 ${PYSITELIB}/myhdl/conversion/__init__.pyc
 ${PYSITELIB}/myhdl/conversion/__init__.pyo
@@ -124,6 +136,14 @@ share/myhdl/cosimulation/icarus/test/inc
 share/myhdl/cosimulation/icarus/test/tb_test.v
 share/myhdl/cosimulation/icarus/test/test.py
 share/myhdl/cosimulation/icarus/test/test_all.py
+share/myhdl/cosimulation/icarus/test/test_gray.py
+share/myhdl/cosimulation/modelsim-win/Makefile
+share/myhdl/cosimulation/modelsim-win/myhdl_vpi.c
+share/myhdl/cosimulation/modelsim-win/test/bin2gray.py
+share/myhdl/cosimulation/modelsim-win/test/dff.py
+share/myhdl/cosimulation/modelsim-win/test/dff_clkout.py
+share/myhdl/cosimulation/modelsim-win/test/inc.py
+share/myhdl/cosimulation/modelsim-win/test/test_all.py
 share/myhdl/cosimulation/modelsim/Makefile
 share/myhdl/cosimulation/modelsim/myhdl_vpi.c
 share/myhdl/cosimulation/modelsim/test/bin2gray.py

Index: pkgsrc/cad/py-MyHDL/distinfo
diff -u pkgsrc/cad/py-MyHDL/distinfo:1.9 pkgsrc/cad/py-MyHDL/distinfo:1.10
--- pkgsrc/cad/py-MyHDL/distinfo:1.9    Sun Oct  9 03:15:57 2016
+++ pkgsrc/cad/py-MyHDL/distinfo        Thu Apr 12 15:08:58 2018
@@ -1,6 +1,6 @@
-$NetBSD: distinfo,v 1.9 2016/10/09 03:15:57 kamil Exp $
+$NetBSD: distinfo,v 1.10 2018/04/12 15:08:58 mef Exp $
 
-SHA1 (myhdl-0.9.0.tar.gz) = 90ee6ab6983d4c11a30a6cca5c749e4affdd8ff1
-RMD160 (myhdl-0.9.0.tar.gz) = 1aac0472829b8a3b171364ed3c85fd9e87a41537
-SHA512 (myhdl-0.9.0.tar.gz) = 6204b1dec7bf16e44e313eff5a76243f64b7f08639a7ca81d621785f022120be37e85e4f8f35a4bb19f05bbfcceb7933f5acbacd71981bd05a87d34fdd71d32d
-Size (myhdl-0.9.0.tar.gz) = 463038 bytes
+SHA1 (myhdl-0.10.tar.gz) = d766a1a556e9dce23af07d1b378fbcc6e3b86494
+RMD160 (myhdl-0.10.tar.gz) = 234d3f3c5d2d84e548e317e1b85bc28efbfd7b14
+SHA512 (myhdl-0.10.tar.gz) = b250c8b09a2cfbd2a70da60d567c8bcb09747c3e8df536cdd28ad49a8a6fbe5a28395295a6ed6046ced745b617fb3804ceb0f83d9b34db7c70701148ae7db25b
+Size (myhdl-0.10.tar.gz) = 1205466 bytes

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