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CVS commit: pkgsrc/sysutils/u-boot
Module Name: pkgsrc
Committed By: mrg
Date: Fri Feb 11 21:46:14 UTC 2022
Added Files:
pkgsrc/sysutils/u-boot: distinfo-2022.01
pkgsrc/sysutils/u-boot/patches-2022.01:
patch-arch_arm_lib_interrupts__64.c
patch-arch_arm_mach-rockchip_rk3399_rk3399.c
patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c
patch-configs_pinebook-pro-rk3399_defconfig
patch-configs_rock64-rk3328_defconfig
patch-configs_rockpro64-rk3399_defconfig
patch-drivers_pci_pcie__rockchip.c
patch-drivers_usb_host_usb-uclass.c
patch-include_config_distro_bootcmd.h
patch-include_configs_rockchip-common.h
patch-include_configs_rockpro64_rk3399.h
Log Message:
add support for u-boot 2022.01. tested with rockpro64 and pinebookpro.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 pkgsrc/sysutils/u-boot/distinfo-2022.01
cvs rdiff -u -r0 -r1.1 \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_lib_interrupts__64.c \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_mach-rockchip_rk3399_rk3399.c \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_pinebook-pro-rk3399_defconfig \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rock64-rk3328_defconfig \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rockpro64-rk3399_defconfig \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_pci_pcie__rockchip.c \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_usb_host_usb-uclass.c \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_config_distro_bootcmd.h \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockchip-common.h \
pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockpro64_rk3399.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: pkgsrc/sysutils/u-boot/distinfo-2022.01
diff -u /dev/null pkgsrc/sysutils/u-boot/distinfo-2022.01:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/distinfo-2022.01 Fri Feb 11 21:46:14 2022
@@ -0,0 +1,16 @@
+$NetBSD: distinfo-2022.01,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+BLAKE2s (u-boot-2022.01.tar.bz2) = 54855aa008e78886dd48a25042eebedb1aee301571e578325131ed93d248c329
+SHA512 (u-boot-2022.01.tar.bz2) = d83c62bd8f0f51664d2aca329a3ce1379cfd1dfff439dccd6cfc2cb33cfef89a2b01855c97716f591b5550bfdf99e2f3aef7efa33f2e7834c820648f9eef3825
+Size (u-boot-2022.01.tar.bz2) = 17449627 bytes
+SHA1 (patch-arch_arm_lib_interrupts__64.c) = 708be481a01b84c6c69d88465adf898b659dbeab
+SHA1 (patch-arch_arm_mach-rockchip_rk3399_rk3399.c) = caa4068c635eaef5997501e154ec5cb11dcbf490
+SHA1 (patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c) = 49954716240e93b33e13288f92b14f527ba15bdf
+SHA1 (patch-configs_pinebook-pro-rk3399_defconfig) = 6f9ddd87ef1486fa0785b2f00c6819ace1436853
+SHA1 (patch-configs_rock64-rk3328_defconfig) = 44c0131d36fbc0bad769104ce07bdab9ae605bbd
+SHA1 (patch-configs_rockpro64-rk3399_defconfig) = d42aba165cb4aca635e514177f43bffacfa8ace5
+SHA1 (patch-drivers_pci_pcie__rockchip.c) = 5ead0933261b2cef81cd317df478e47ecc0382d4
+SHA1 (patch-drivers_usb_host_usb-uclass.c) = 754504a9dc08f888a4ef09f5ccc3cb56b5ce297a
+SHA1 (patch-include_config_distro_bootcmd.h) = d37da930903d9d80829ac3cd0da98334057b6188
+SHA1 (patch-include_configs_rockchip-common.h) = d9aa111ec38f2f8ad64c45d42d3bc5519e27382d
+SHA1 (patch-include_configs_rockpro64_rk3399.h) = 7efd0b09cbf627dc59d2a23a76dd6506c9efc4c9
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_lib_interrupts__64.c
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_lib_interrupts__64.c:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_lib_interrupts__64.c Fri Feb 11 21:46:14 2022
@@ -0,0 +1,44 @@
+$NetBSD: patch-arch_arm_lib_interrupts__64.c,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+u-boot-rockpro64: fix broken PCI config space handling:
+
+- Program bus number into the ECAM decoder for each access
+- Use type 1 PCI config cycles for config spaces behind bridge
+- Add a platform specific hack to the synchronous exception handler
+ to deal with PCI-e subsystem triggering data aborts when probing
+ nonexistent PCI devices.
+- properly delay after deasserting reset for downstream devices to
+ have time to initialize.
+
+Allows booting from PCI devices behind bridges and probing
+devices other than 0:0:0 and 1:0:0.
+
+--- arch/arm/lib/interrupts_64.c.orig 2021-07-05 15:11:28.000000000 +0000
++++ arch/arm/lib/interrupts_64.c
+@@ -111,11 +111,26 @@ void do_bad_error(struct pt_regs *pt_reg
+ panic("Resetting CPU ...\n");
+ }
+
++#ifdef CONFIG_ROCKCHIP_RK3399
++extern volatile int rockchip_pcie_expect_data_abort;
++extern volatile int rockchip_pcie_got_data_abort;
++#endif
+ /*
+ * do_sync handles the Synchronous Abort exception.
+ */
+ void do_sync(struct pt_regs *pt_regs, unsigned int esr)
+ {
++#ifdef CONFIG_ROCKCHIP_RK3399
++ if ((esr >> 26) == 0x25 && rockchip_pcie_expect_data_abort) {
++ /*
++ * Data Abort taken without a change in Exception level.
++ * This happens when probing nonexistent PCI-e devices.
++ */
++ rockchip_pcie_got_data_abort = 1;
++ pt_regs->elr += 4; /* skip faulting insn */
++ return;
++ }
++#endif
+ efi_restore_gd();
+ printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_mach-rockchip_rk3399_rk3399.c
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_mach-rockchip_rk3399_rk3399.c:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-arch_arm_mach-rockchip_rk3399_rk3399.c Fri Feb 11 21:46:14 2022
@@ -0,0 +1,52 @@
+$NetBSD: patch-arch_arm_mach-rockchip_rk3399_rk3399.c,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+adjusted by mrg to restrict to CONFIG_TARGET_PINEBOOK_PRO_RK3399.
+
+
+Author: dhivael <dhivael.git@eno.space>
+Date: Sat Jan 11 15:04:46 2020 +0100
+
+ rk3399: light pinebook power and standby leds during early boot
+
+ this is a hack, but it works for now.
+
+
+--- arch/arm/mach-rockchip/rk3399/rk3399.c.orig 2021-04-05 08:03:29.000000000 -0700
++++ arch/arm/mach-rockchip/rk3399/rk3399.c 2021-05-08 00:46:34.547804408 -0700
+@@ -20,6 +20,8 @@
+ #include <asm/arch-rockchip/hardware.h>
+ #include <linux/bitops.h>
+ #include <power/regulator.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -122,6 +124,9 @@
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+ #endif
++#ifdef CONFIG_TARGET_PINEBOOK_PRO_RK3399
++ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
++#endif
+
+ #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+ /* Enable early UART0 on the RK3399 */
+@@ -154,6 +159,17 @@
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
+ #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
++#ifdef CONFIG_TARGET_PINEBOOK_PRO_RK3399
++
++ {
++ // set GPIO0_A2/B3 to GPIO_ACTIVE_HIGH
++ // set GPIO0_A2/B3 to OUTPUT
++ int mask = (1UL << RK_PA2) | (1UL << RK_PB3);
++ setbits_le32(&gpio->swport_dr, mask);
++ setbits_le32(&gpio->swport_ddr, mask);
++ }
++#endif
++
+ /* Enable early UART2 channel C on the RK3399 */
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C3_SEL_MASK,
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c Fri Feb 11 21:46:14 2022
@@ -0,0 +1,60 @@
+$NetBSD: patch-board_pine64_pinebook-pro-rk3399_pinebook-pro-rk3399.c,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Fix panel reset.
+
+
+From 352cb7b28bf4a16330f148043e8d10b0141bbfcb Mon Sep 17 00:00:00 2001
+From: Arnaud Patard <arnaud.patard%rtp-net.org@localhost>
+Date: Wed, 8 Jul 2020 21:43:36 -0400
+Subject: [PATCH 4/4] PBP: Fix panel reset
+
+On warm reset, the pinebook pro panel is not working correctly.
+The issue is not yet debugged so, for now, this hack seems to be
+enough. It toggles the GPIO1_C6 gpio [ LCDVCC_EN signal in the
+schematics ] used by the vcc3v3_panel regulator.
+
+There's no gpio_request, since the gpio is already in use at this
+stage, so it can only fail.
+
+Origin: http://people.hupstream.com/~rtp/pbp/20200706/patches/hack-reset.patch
+
+
+--- board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c.orig 2021-04-26 17:53:51.000000000 -0700
++++ board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c 2021-05-08 15:36:55.355143117 -0700
+@@ -7,13 +7,15 @@
+ #include <common.h>
+ #include <dm.h>
+ #include <syscon.h>
++#include <linux/delay.h>
++#include <asm/gpio.h>
+ #include <asm/io.h>
+ #include <asm/arch-rockchip/clock.h>
+ #include <asm/arch-rockchip/grf_rk3399.h>
++#include <asm/arch-rockchip/gpio.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <asm/arch-rockchip/misc.h>
+ #include <power/regulator.h>
+-
+ #define GRF_IO_VSEL_BT565_SHIFT 0
+ #define PMUGRF_CON0_VSEL_SHIFT 8
+
+@@ -59,6 +61,7 @@
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
++ unsigned int gpio;
+
+ setup_iodomain();
+
+@@ -70,6 +73,11 @@
+ if (ret)
+ return ret;
+
++ gpio_lookup_name("B22", NULL, NULL, &gpio);
++ gpio_direction_output(gpio, 0);
++ udelay(500000);
++ gpio_direction_output(gpio, 1);
++
+ return ret;
+ }
+ #endif
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_pinebook-pro-rk3399_defconfig
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_pinebook-pro-rk3399_defconfig:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_pinebook-pro-rk3399_defconfig Fri Feb 11 21:46:14 2022
@@ -0,0 +1,14 @@
+$NetBSD: patch-configs_pinebook-pro-rk3399_defconfig,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Load u-boot from 256KB.
+
+--- configs/pinebook-pro-rk3399_defconfig.orig 2021-07-05 08:11:28.000000000 -0700
++++ configs/pinebook-pro-rk3399_defconfig 2021-07-25 14:05:30.629973309 -0700
+@@ -3,6 +3,7 @@
+ CONFIG_SYS_TEXT_BASE=0x00200000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_ENV_SIZE=0x8000
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+ CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
+ CONFIG_ROCKCHIP_RK3399=y
+ CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rock64-rk3328_defconfig
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rock64-rk3328_defconfig:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rock64-rk3328_defconfig Fri Feb 11 21:46:14 2022
@@ -0,0 +1,14 @@
+$NetBSD: patch-configs_rock64-rk3328_defconfig,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Load u-boot from 256KB.
+
+--- configs/rock64-rk3328_defconfig.orig 2022-01-10 10:46:34.000000000 -0800
++++ configs/rock64-rk3328_defconfig 2022-02-07 02:26:32.821429380 -0800
+@@ -1,6 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_SKIP_LOWLEVEL_INIT=y
+ CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+ CONFIG_SYS_TEXT_BASE=0x00200000
+ CONFIG_SPL_GPIO=y
+ CONFIG_NR_DRAM_BANKS=1
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rockpro64-rk3399_defconfig
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rockpro64-rk3399_defconfig:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-configs_rockpro64-rk3399_defconfig Fri Feb 11 21:46:14 2022
@@ -0,0 +1,29 @@
+$NetBSD: patch-configs_rockpro64-rk3399_defconfig,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Load u-boot from 256KB.
+Enable AHCI and Silicon Image PCIe SATA controllers.
+
+--- configs/rockpro64-rk3399_defconfig.orig 2022-01-10 10:46:34.000000000 -0800
++++ configs/rockpro64-rk3399_defconfig 2022-02-07 17:35:17.409379259 -0800
+@@ -1,6 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_SKIP_LOWLEVEL_INIT=y
+ CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+ CONFIG_SYS_TEXT_BASE=0x00200000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_ENV_SIZE=0x8000
+@@ -63,6 +64,13 @@
+ CONFIG_DEBUG_UART_SHIFT=2
+ CONFIG_ROCKCHIP_SPI=y
+ CONFIG_SYSRESET=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SATA=y
++CONFIG_SATA_SIL=y
++CONFIG_SCSI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_DM_SCSI=y
+ CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_pci_pcie__rockchip.c
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_pci_pcie__rockchip.c:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_pci_pcie__rockchip.c Fri Feb 11 21:46:14 2022
@@ -0,0 +1,134 @@
+$NetBSD: patch-drivers_pci_pcie__rockchip.c,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+u-boot-rockpro64: fix broken PCI config space handling:
+
+- Program bus number into the ECAM decoder for each access
+- Use type 1 PCI config cycles for config spaces behind bridge
+- Add a platform specific hack to the synchronous exception handler
+ to deal with PCI-e subsystem triggering data aborts when probing
+ nonexistent PCI devices.
+- properly delay after deasserting reset for downstream devices to
+ have time to initialize.
+
+Allows booting from PCI devices behind bridges and probing
+devices other than 0:0:0 and 1:0:0.
+
+--- drivers/pci/pcie_rockchip.c.orig 2021-07-05 15:11:28.000000000 +0000
++++ drivers/pci/pcie_rockchip.c
+@@ -73,6 +73,8 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
+ #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+
++#define PCIE_ATR_REGION0_PASS_BITS (20 - 1)
++
+ struct rockchip_pcie {
+ fdt_addr_t axi_base;
+ fdt_addr_t apb_base;
+@@ -103,13 +105,15 @@ struct rockchip_pcie {
+
+ static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
+ {
+- unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int func = PCI_FUNC(bdf);
+
+- return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
++ return (dev << 15) | (func << 12) | (offset & ~0x3);
+ }
+
++volatile int rockchip_pcie_expect_data_abort;
++volatile int rockchip_pcie_got_data_abort;
++
+ static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+@@ -127,8 +131,33 @@ static int rockchip_pcie_rd_conf(const s
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
++ writel((bus << 20) | PCIE_ATR_REGION0_PASS_BITS,
++ priv->apb_base + PCIE_ATR_OB_ADDR0(0));
++ writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
++ priv->apb_base + PCIE_ATR_OB_DESC0(0));
++ dsb();
+ value = readl(priv->axi_base + where);
+ *valuep = pci_conv_32_to_size(value, offset, size);
++ dsb();
++ return 0;
++ }
++
++ if (bus > priv->first_busno + 1) {
++ writel((bus << 20) | PCIE_ATR_REGION0_PASS_BITS,
++ priv->apb_base + PCIE_ATR_OB_ADDR0(0));
++ writel(PCIE_ATR_HDR_CFG_TYPE1 | PCIE_ATR_HDR_RID,
++ priv->apb_base + PCIE_ATR_OB_DESC0(0));
++ dsb();
++ rockchip_pcie_got_data_abort = 0;
++ rockchip_pcie_expect_data_abort = 1;
++ value = readl(priv->axi_base + where);
++ rockchip_pcie_expect_data_abort = 0;
++ if (rockchip_pcie_got_data_abort) {
++ *valuep = pci_get_ff(size);
++ return 0;
++ }
++ *valuep = pci_conv_32_to_size(value, offset, size);
++ dsb();
+ return 0;
+ }
+
+@@ -155,9 +184,28 @@ static int rockchip_pcie_wr_conf(struct
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
++ writel((bus << 20) | PCIE_ATR_REGION0_PASS_BITS,
++ priv->apb_base + PCIE_ATR_OB_ADDR0(0));
++ writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
++ priv->apb_base + PCIE_ATR_OB_DESC0(0));
++ dsb();
+ old = readl(priv->axi_base + where);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, priv->axi_base + where);
++ dsb();
++ return 0;
++ }
++
++ if (bus > priv->first_busno + 1) {
++ writel((bus << 20) | PCIE_ATR_REGION0_PASS_BITS,
++ priv->apb_base + PCIE_ATR_OB_ADDR0(0));
++ writel(PCIE_ATR_HDR_CFG_TYPE1 | PCIE_ATR_HDR_RID,
++ priv->apb_base + PCIE_ATR_OB_DESC0(0));
++ dsb();
++ old = readl(priv->axi_base + where);
++ value = pci_conv_size_to_32(old, value, offset, size);
++ writel(value, priv->axi_base + where);
++ dsb();
+ return 0;
+ }
+
+@@ -173,7 +221,7 @@ static int rockchip_pcie_atr_init(struct
+ int i, region;
+
+ /* Use region 0 to map PCI configuration space. */
+- writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
++ writel(PCIE_ATR_REGION0_PASS_BITS, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
+ writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
+ priv->apb_base + PCIE_ATR_OB_DESC0(0));
+@@ -343,6 +391,8 @@ static int rockchip_pcie_init_port(struc
+ goto err_power_off_phy;
+ }
+
++ mdelay(20); /* 20 ms according to PCI-e BS "Conventional Reset" */
++
+ /* Enable Gen1 training */
+ writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ priv->apb_base + PCIE_CLIENT_CONFIG);
+@@ -378,6 +428,8 @@ static int rockchip_pcie_init_port(struc
+ goto err_power_off_phy;
+ }
+
++ mdelay(80); /* wait 100 ms before CSR accesses. Already waited 20. */
++
+ return 0;
+
+ err_power_off_phy:
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_usb_host_usb-uclass.c
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_usb_host_usb-uclass.c:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-drivers_usb_host_usb-uclass.c Fri Feb 11 21:46:14 2022
@@ -0,0 +1,34 @@
+$NetBSD: patch-drivers_usb_host_usb-uclass.c,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Disable USB. Hangs in usb_stop() / 'usb stop', if started.
+
+Should be obsoleted by upstream:
+ https://source.denx.de/u-boot/u-boot/-/commit/226fce6108fe364e35f3eb9a84ff1a7ec93727ce
+but this breaks the USB3 port on RockPro64 and Pinebook Pro.
+
+--- drivers/usb/host/usb-uclass.c.orig 2021-07-05 08:11:28.000000000 -0700
++++ drivers/usb/host/usb-uclass.c 2021-07-24 12:49:38.736439999 -0700
+@@ -173,6 +173,15 @@
+
+ int usb_stop(void)
+ {
++#if 1
++ /*
++ * XXXMRG
++ *
++ * This hangs when called either from EFI's ExitBootServices() or
++ * explicit call to usb_stop(), say "usb stop" from the command prompt.
++ */
++ printf("Not doing usb_stop().\n");
++#else
+ struct udevice *bus;
+ struct udevice *rh;
+ struct uclass *uc;
+@@ -211,6 +220,7 @@
+ usb_started = 0;
+
+ return err;
++#endif
+ }
+
+ static void usb_scan_bus(struct udevice *bus, bool recurse)
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_config_distro_bootcmd.h
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_config_distro_bootcmd.h:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_config_distro_bootcmd.h Fri Feb 11 21:46:14 2022
@@ -0,0 +1,35 @@
+$NetBSD: patch-include_config_distro_bootcmd.h,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Fix bug in BOOTENV_SET_SCSI_NEED_INIT that skips the SCSI scan.
+Probably fix virtio as well.
+
+--- include/config_distro_bootcmd.h.orig 2022-01-10 10:46:34.000000000 -0800
++++ include/config_distro_bootcmd.h 2022-02-09 01:21:58.541415139 -0800
+@@ -217,11 +217,11 @@
+
+ #ifdef CONFIG_SCSI
+ #define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+-#define BOOTENV_SET_SCSI_NEED_INIT "scsi_need_init=; "
++#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
+ #define BOOTENV_SHARED_SCSI \
+ "scsi_init=" \
+ "if ${scsi_need_init}; then " \
+- "scsi_need_init=false; " \
++ "setenv scsi_need_init false; " \
+ "scsi scan; " \
+ "fi\0" \
+ \
+@@ -295,11 +295,11 @@
+
+ #ifdef CONFIG_CMD_VIRTIO
+ #define BOOTENV_RUN_VIRTIO_INIT "run virtio_init; "
+-#define BOOTENV_SET_VIRTIO_NEED_INIT "virtio_need_init=; "
++#define BOOTENV_SET_VIRTIO_NEED_INIT "setenv virtio_need_init; "
+ #define BOOTENV_SHARED_VIRTIO \
+ "virtio_init=" \
+ "if ${virtio_need_init}; then " \
+- "virtio_need_init=false; " \
++ "setenv virtio_need_init false; " \
+ "virtio scan; " \
+ "fi\0" \
+ \
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockchip-common.h
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockchip-common.h:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockchip-common.h Fri Feb 11 21:46:14 2022
@@ -0,0 +1,53 @@
+$NetBSD: patch-include_configs_rockchip-common.h,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Add SCSI/AHCI support.
+Default to booting from SD, USB, EMMC, NVME, SCSI, PXE, DHCP and then SF.
+
+--- include/configs/rockchip-common.h.orig 2022-01-10 10:46:34.000000000 -0800
++++ include/configs/rockchip-common.h 2022-02-07 02:27:47.781052660 -0800
+@@ -16,11 +16,10 @@
+
+ /* First try to boot from SD (index 1), then eMMC (index 0) */
+ #if CONFIG_IS_ENABLED(CMD_MMC)
+- #define BOOT_TARGET_MMC(func) \
+- func(MMC, mmc, 1) \
+- func(MMC, mmc, 0)
++ #define BOOT_TARGET_MMC(func, idx) \
++ func(MMC, mmc, idx)
+ #else
+- #define BOOT_TARGET_MMC(func)
++ #define BOOT_TARGET_MMC(func, idx)
+ #endif
+
+ #if CONFIG_IS_ENABLED(CMD_NVME)
+@@ -53,18 +52,27 @@
+ #define BOOT_TARGET_SF(func)
+ #endif
+
++#if CONFIG_IS_ENABLED(CMD_SCSI)
++ #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
++#else
++ #define BOOT_TARGET_SCSI(func)
++#endif
++
+ #ifdef CONFIG_ROCKCHIP_RK3399
+ #define BOOT_TARGET_DEVICES(func) \
+- BOOT_TARGET_MMC(func) \
+- BOOT_TARGET_NVME(func) \
++ BOOT_TARGET_MMC(func, 1) \
+ BOOT_TARGET_USB(func) \
++ BOOT_TARGET_MMC(func, 0) \
++ BOOT_TARGET_NVME(func) \
++ BOOT_TARGET_SCSI(func) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func) \
+ BOOT_TARGET_SF(func)
+ #else
+ #define BOOT_TARGET_DEVICES(func) \
+- BOOT_TARGET_MMC(func) \
++ BOOT_TARGET_MMC(func, 1) \
+ BOOT_TARGET_USB(func) \
++ BOOT_TARGET_MMC(func, 0) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
+ #endif
Index: pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockpro64_rk3399.h
diff -u /dev/null pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockpro64_rk3399.h:1.1
--- /dev/null Fri Feb 11 21:46:14 2022
+++ pkgsrc/sysutils/u-boot/patches-2022.01/patch-include_configs_rockpro64_rk3399.h Fri Feb 11 21:46:14 2022
@@ -0,0 +1,20 @@
+$NetBSD: patch-include_configs_rockpro64_rk3399.h,v 1.1 2022/02/11 21:46:14 mrg Exp $
+
+Add CONFIG_SCSI support.
+
+--- include/configs/rockpro64_rk3399.h.orig 2021-04-26 17:53:51.000000000 -0700
++++ include/configs/rockpro64_rk3399.h 2021-05-22 16:57:19.869714755 -0700
+@@ -17,4 +17,13 @@
+
+ #define CONFIG_USB_OHCI_NEW
+ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
++
++#if defined(CONFIG_SCSI) && 0
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SYS_SCSI_MAX_DEVICE 4
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
++#define CONFIG_SYS_SCSI_MAX_LUN 1
++#define CONFIG_SYS_SATA_MAX_DEVICE 4
++#endif
++
+ #endif
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