CVS commit: pkgsrc/www/firefox

["Tobias Nygren" <tnn%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   tnn
Date:           Sun Aug 20 21:41:54 UTC 2023

Modified Files:
        pkgsrc/www/firefox: distinfo
Added Files:
        pkgsrc/www/firefox/patches: patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp

Log Message:
firefox: fix ICache flushing in js::jit for NetBSD/aarch64

Makes the browser somewhat usable again.


To generate a diff of this commit:
cvs rdiff -u -r1.505 -r1.506 pkgsrc/www/firefox/distinfo
cvs rdiff -u -r0 -r1.1 \
    pkgsrc/www/firefox/patches/patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/www/firefox/distinfo
diff -u pkgsrc/www/firefox/distinfo:1.505 pkgsrc/www/firefox/distinfo:1.506
--- pkgsrc/www/firefox/distinfo:1.505   Sun Aug 20 09:31:25 2023
+++ pkgsrc/www/firefox/distinfo Sun Aug 20 21:41:54 2023
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.505 2023/08/20 09:31:25 tnn Exp $
+$NetBSD: distinfo,v 1.506 2023/08/20 21:41:54 tnn Exp $
 
 BLAKE2s (firefox-116.0.3.source.tar.xz) = 22e0a147eaeab2c65516f3bd7277ba7ff45e232d7f2ba56179f6f5a6c88bd6c0
 SHA512 (firefox-116.0.3.source.tar.xz) = 194c50e9ba5a918c37fbef8cd72ffb98e5e9f51955d8172b6666a758b5f20777ca0a7f79dff0328305fb6dafefb102ab002e326f47d0965a4dc6d3e9287c42b9
@@ -19,6 +19,7 @@ SHA1 (patch-gfx_wr_swgl_build.rs) = df6e
 SHA1 (patch-ipc_chromium_src_base_message__pump__libevent.cc) = 298642a3527804115b398fb7904a3596962932e3
 SHA1 (patch-ipc_chromium_src_base_platform__thread__posix.cc) = 753bb4e90758f5b42a51bbc073b328de673988cf
 SHA1 (patch-ipc_glue_GeckoChildProcessHost.cpp) = 6cdd0fe60455eab8f9846257c2bfea207f19478b
+SHA1 (patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp) = acb31066cd407e9e08cb7a7b6c4d0e702f5a8107
 SHA1 (patch-js_src_jit_FlushICache.cpp) = d1e611eaf7d7be22abfac6b39fbcd99df3570e47
 SHA1 (patch-js_src_util_NativeStack.cpp) = a0a16d8d8d78d3cc3f4d2a508586f1a7821f7dba
 SHA1 (patch-media_ffvpx_libavutil_arm_bswap.h) = de58daa0fd23d4fec50426602b65c9ea5862558a

Added files:

Index: pkgsrc/www/firefox/patches/patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp
diff -u /dev/null pkgsrc/www/firefox/patches/patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp:1.1
--- /dev/null   Sun Aug 20 21:41:54 2023
+++ pkgsrc/www/firefox/patches/patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp      Sun Aug 20 21:41:54 2023
@@ -0,0 +1,24 @@
+$NetBSD: patch-js-src-jit-arm64-vixl-MozCpu-vixl.cpp,v 1.1 2023/08/20 21:41:54 tnn Exp $
+
+Add NetBSD support.
+
+--- js/src/jit/arm64/vixl/MozCpu-vixl.cpp.orig 2023-08-15 20:31:20.000000000 +0000
++++ js/src/jit/arm64/vixl/MozCpu-vixl.cpp
+@@ -68,7 +68,7 @@ void CPU::SetUp() {
+ 
+ 
+ uint32_t CPU::GetCacheType() {
+-#if defined(__aarch64__) && (defined(__linux__) || defined(__android__))
++#if defined(__aarch64__) && (defined(__linux__) || defined(__android__) || defined(__NetBSD__))
+   uint64_t cache_type_register;
+   // Copy the content of the cache type register to a core register.
+   __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
+@@ -110,7 +110,7 @@ void CPU::EnsureIAndDCacheCoherency(void
+   FlushInstructionCache(GetCurrentProcess(), address, length);
+ #elif defined(XP_DARWIN)
+   sys_icache_invalidate(address, length);
+-#elif defined(__aarch64__) && (defined(__linux__) || defined(__android__))
++#elif defined(__aarch64__) && (defined(__linux__) || defined(__android__) || defined(__NetBSD__))
+   // Implement the cache synchronisation for all targets where AArch64 is the
+   // host, even if we're building the simulator for an AAarch64 host. This
+   // allows for cases where the user wants to simulate code as well as run it