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CVS commit: pkgsrc/www/palemoon
Module Name: pkgsrc
Committed By: nia
Date: Mon Jul 29 18:13:49 UTC 2024
Modified Files:
pkgsrc/www/palemoon: Makefile distinfo
Added Files:
pkgsrc/www/palemoon/patches:
patch-platform_ipc_chromium_src_base_atomicops.h
patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h
patch-platform_media_libaom_config_linux_arm_config_aom__config.h
patch-platform_media_libtheora_moz.build
patch-platform_media_libvpx_config_linux_arm_vpx__config.h
patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h
patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h
patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp
patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp
Log Message:
palemoon: Fix building on NetBSD/earmv7hf
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 pkgsrc/www/palemoon/Makefile
cvs rdiff -u -r1.4 -r1.5 pkgsrc/www/palemoon/distinfo
cvs rdiff -u -r0 -r1.1 \
pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops.h \
pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h \
pkgsrc/www/palemoon/patches/patch-platform_media_libaom_config_linux_arm_config_aom__config.h \
pkgsrc/www/palemoon/patches/patch-platform_media_libtheora_moz.build \
pkgsrc/www/palemoon/patches/patch-platform_media_libvpx_config_linux_arm_vpx__config.h \
pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h \
pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h \
pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp \
pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: pkgsrc/www/palemoon/Makefile
diff -u pkgsrc/www/palemoon/Makefile:1.2 pkgsrc/www/palemoon/Makefile:1.3
--- pkgsrc/www/palemoon/Makefile:1.2 Sat Jul 27 14:04:15 2024
+++ pkgsrc/www/palemoon/Makefile Mon Jul 29 18:13:48 2024
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.2 2024/07/27 14:04:15 abs Exp $
+# $NetBSD: Makefile,v 1.3 2024/07/29 18:13:48 nia Exp $
# for build instructions see
# https://developer.palemoon.org/build/linux/
@@ -91,6 +91,10 @@ CWRAPPERS_APPEND.ld+= ${LINKER_RPATH_FLA
TOOL_DEPENDS+= yasm>=1.1:../../devel/yasm
.endif
+.if ${MACHINE_PLATFORM:MNetBSD-*-earm*}
+LDFLAGS+= -Wl,--no-keep-memory
+.endif
+
INSTALLATION_DIRS+= share/applications
INSTALLATION_DIRS+= share/icons/hicolor/16x16/apps
INSTALLATION_DIRS+= share/icons/hicolor/32x32/apps
Index: pkgsrc/www/palemoon/distinfo
diff -u pkgsrc/www/palemoon/distinfo:1.4 pkgsrc/www/palemoon/distinfo:1.5
--- pkgsrc/www/palemoon/distinfo:1.4 Mon Jul 29 13:55:54 2024
+++ pkgsrc/www/palemoon/distinfo Mon Jul 29 18:13:48 2024
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.4 2024/07/29 13:55:54 nia Exp $
+$NetBSD: distinfo,v 1.5 2024/07/29 18:13:48 nia Exp $
BLAKE2s (palemoon-33.2.1/palemoon.tar.gz) = 5963bc12be28b07ded0558bb20bc27108f3aebd1895e4730e6a6ac2013a7ae9d
SHA512 (palemoon-33.2.1/palemoon.tar.gz) = 72e6a4858af679a88fd079ed28020a8d845366d0b3ea5cb00b5a17dd9d6b7a4171397ceaa156b3e9f1d185e39e7ba8c82864641bd21f704350ef4b6473cc693d
@@ -14,11 +14,20 @@ SHA1 (patch-platform_build_moz.build) =
SHA1 (patch-platform_gfx_angle_src_libANGLE_renderer_gl_glx_FunctionsGLX.cpp) = 502d79eb3ef41e08328bbac9fbb5048b96660bbb
SHA1 (patch-platform_gfx_gl_GLContextProviderGLX.cpp) = 56685c8c5f176b0660a6208437d81085f6ad00a5
SHA1 (patch-platform_intl_icu_source_configure) = 87d19e9212b4340d9b052b5a89be84432ad1cff2
+SHA1 (patch-platform_ipc_chromium_src_base_atomicops.h) = ab4b489e9f9c22a861a275924ef34a909d210828
+SHA1 (patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h) = f33b6c391689c52d0a6855e29ff25d863a7f15e5
SHA1 (patch-platform_js_src_jit_ProcessExecutableMemory.cpp) = 5cf5a2205a2b38fb8785e6c255231fbcdbd13949
SHA1 (patch-platform_js_src_vm_ArrayBufferObject.cpp) = 652db4b78ecaba840c0cba945b4af39a6b1362b9
+SHA1 (patch-platform_media_libaom_config_linux_arm_config_aom__config.h) = 69ef22fe9892c2288accb6eb00b4533d8cee0299
SHA1 (patch-platform_media_libcubeb_src_cubeb__sun.c) = ce27774d772d65fa60b6be5bee82fbe4f787f3d1
SHA1 (patch-platform_media_libcubeb_src_moz.build) = 5f9f7656bf9d251edb395cb19fae8cd614c0b287
+SHA1 (patch-platform_media_libtheora_moz.build) = a7bad662dabb87c6a85542a4a50f8ed693064bc6
+SHA1 (patch-platform_media_libvpx_config_linux_arm_vpx__config.h) = a580208cd342d7dc27985118e1707772e0cccf02
SHA1 (patch-platform_old-configure.in) = 05711cd91f7adca8c7325d01dc6e6553ce5bedb5
+SHA1 (patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h) = 73b57772d29b0567c0aa1faea8a3f345dbc0488a
+SHA1 (patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h) = 2a5ccc95fb5860b1be97947f3aee8307f4a25bc1
SHA1 (patch-platform_security_generate__mapfile.py) = ae457a8e85c4ce95014dff442b8afd0e20ded543
+SHA1 (patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp) = 5b6a5c6eea2668cc5eaaf775400c382114876d86
+SHA1 (patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp) = de7188f7ac09fd3d4a65968a12ae324b3a0415c4
SHA1 (patch-platform_toolkit_xre_glxtest.cpp) = f8bd5705f5cf87651df59ba22f4566136e3bc4ef
SHA1 (patch-platform_toolkit_xre_nsX11ErrorHandler.cpp) = 164d93a5b1aaeba15b524fdaef0483b4a9400ac1
Added files:
Index: pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,15 @@
+$NetBSD: patch-platform_ipc_chromium_src_base_atomicops.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Fixes for NetBSD/arm, taken from www/firefox52
+
+--- platform/ipc/chromium/src/base/atomicops.h.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/ipc/chromium/src/base/atomicops.h
+@@ -46,7 +46,7 @@ typedef int64_t Atomic64;
+
+ // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or
+ // Atomic64 routines below, depending on your architecture.
+-#ifdef OS_OPENBSD
++#if defined(OS_OPENBSD) || (defined(OS_NETBSD) && defined(ARCH_CPU_ARM_FAMILY))
+ #ifdef ARCH_CPU_64_BITS
+ typedef Atomic64 AtomicWord;
+ #else
Index: pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,92 @@
+$NetBSD: patch-platform_ipc_chromium_src_base_atomicops__internals__arm__gcc.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Fixes for NetBSD/arm, taken from www/firefox52
+
+--- platform/ipc/chromium/src/base/atomicops_internals_arm_gcc.h.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/ipc/chromium/src/base/atomicops_internals_arm_gcc.h
+@@ -13,44 +13,19 @@
+ namespace base {
+ namespace subtle {
+
+-// 0xffff0fc0 is the hard coded address of a function provided by
+-// the kernel which implements an atomic compare-exchange. On older
+-// ARM architecture revisions (pre-v6) this may be implemented using
+-// a syscall. This address is stable, and in active use (hard coded)
+-// by at least glibc-2.7 and the Android C library.
+-typedef Atomic32 (*LinuxKernelCmpxchgFunc)(Atomic32 old_value,
+- Atomic32 new_value,
+- volatile Atomic32* ptr);
+-LinuxKernelCmpxchgFunc pLinuxKernelCmpxchg __attribute__((weak)) =
+- (LinuxKernelCmpxchgFunc) 0xffff0fc0;
+-
+-typedef void (*LinuxKernelMemoryBarrierFunc)(void);
+-LinuxKernelMemoryBarrierFunc pLinuxKernelMemoryBarrier __attribute__((weak)) =
+- (LinuxKernelMemoryBarrierFunc) 0xffff0fa0;
+-
+-
+ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
+ Atomic32 old_value,
+ Atomic32 new_value) {
+- Atomic32 prev_value = *ptr;
+- do {
+- if (!pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr))) {
+- return old_value;
+- }
+- prev_value = *ptr;
+- } while (prev_value == old_value);
+- return prev_value;
++ return __sync_val_compare_and_swap(ptr, old_value, new_value);
+ }
+
+ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
+ Atomic32 new_value) {
+- Atomic32 old_value;
++ Atomic32 prev_value;
+ do {
+- old_value = *ptr;
+- } while (pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr)));
+- return old_value;
++ prev_value = *ptr;
++ } while (!__sync_bool_compare_and_swap(ptr, prev_value, new_value));
++ return prev_value;
+ }
+
+ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
+@@ -60,18 +35,15 @@ inline Atomic32 NoBarrier_AtomicIncremen
+
+ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
+ Atomic32 increment) {
+- for (;;) {
+- // Atomic exchange the old value with an incremented one.
+- Atomic32 old_value = *ptr;
+- Atomic32 new_value = old_value + increment;
+- if (pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr)) == 0) {
+- // The exchange took place as expected.
+- return new_value;
+- }
+- // Otherwise, *ptr changed mid-loop and we need to retry.
+- }
++ Atomic32 old_value;
++ Atomic32 new_value;
+
++ do {
++ // Atomic exchange the old value with an incremented one.
++ old_value = *ptr;
++ new_value = old_value + increment;
++ } while (!__sync_bool_compare_and_swap(ptr, old_value, new_value));
++ return new_value;
+ }
+
+ inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
+@@ -91,7 +63,7 @@ inline void NoBarrier_Store(volatile Ato
+ }
+
+ inline void MemoryBarrier() {
+- pLinuxKernelMemoryBarrier();
++ __sync_synchronize();
+ }
+
+ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
Index: pkgsrc/www/palemoon/patches/patch-platform_media_libaom_config_linux_arm_config_aom__config.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_media_libaom_config_linux_arm_config_aom__config.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_media_libaom_config_linux_arm_config_aom__config.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,19 @@
+$NetBSD: patch-platform_media_libaom_config_linux_arm_config_aom__config.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Runtime CPU detection on ARM is currently unimplemented for anything
+except Linux.
+
+--- platform/media/libaom/config/linux/arm/config/aom_config.h.orig 2024-07-29 11:09:32.665087168 +0000
++++ platform/media/libaom/config/linux/arm/config/aom_config.h
+@@ -59,7 +59,11 @@
+ #define CONFIG_RD_DEBUG 0
+ #define CONFIG_REALTIME_ONLY 0
+ #define CONFIG_RT_ML_PARTITIONING 0
++#ifdef __linux
+ #define CONFIG_RUNTIME_CPU_DETECT 1
++#else
++#define CONFIG_RUNTIME_CPU_DETECT 0
++#endif
+ #define CONFIG_SHARED 0
+ #define CONFIG_SIZE_LIMIT 0
+ #define CONFIG_SPATIAL_RESAMPLING 1
Index: pkgsrc/www/palemoon/patches/patch-platform_media_libtheora_moz.build
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_media_libtheora_moz.build:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_media_libtheora_moz.build Mon Jul 29 18:13:48 2024
@@ -0,0 +1,16 @@
+$NetBSD: patch-platform_media_libtheora_moz.build,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Runtime CPU detection on ARM is currently unimplemented for anything
+except Linux.
+
+--- platform/media/libtheora/moz.build.orig 2024-07-29 10:59:14.581061883 +0000
++++ platform/media/libtheora/moz.build
+@@ -82,7 +82,7 @@ if CONFIG['INTEL_ARCHITECTURE']:
+ 'lib/x86/x86state.c',
+ ]
+
+-if CONFIG['GNU_AS']:
++if CONFIG['GNU_AS'] and CONFIG['OS_ARCH'] == 'Linux':
+ if CONFIG['CPU_ARCH'] == 'arm':
+ SOURCES += [
+ 'lib/arm/armcpu.c',
Index: pkgsrc/www/palemoon/patches/patch-platform_media_libvpx_config_linux_arm_vpx__config.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_media_libvpx_config_linux_arm_vpx__config.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_media_libvpx_config_linux_arm_vpx__config.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,19 @@
+$NetBSD: patch-platform_media_libvpx_config_linux_arm_vpx__config.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Runtime CPU detection on ARM is currently unimplemented for anything
+except Linux.
+
+--- platform/media/libvpx/config/linux/arm/vpx_config.h.orig 2024-07-29 10:28:36.006671626 +0000
++++ platform/media/libvpx/config/linux/arm/vpx_config.h
+@@ -48,7 +48,11 @@
+ #define CONFIG_DEBUG_LIBS 0
+ #define CONFIG_DEQUANT_TOKENS 0
+ #define CONFIG_DC_RECON 0
++#ifdef __linux
+ #define CONFIG_RUNTIME_CPU_DETECT 1
++#else
++#define CONFIG_RUNTIME_CPU_DETECT 0
++#endif
+ #define CONFIG_POSTPROC 0
+ #define CONFIG_VP9_POSTPROC 0
+ #define CONFIG_MULTITHREAD 1
Index: pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,26 @@
+$NetBSD: patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Fixes for NetBSD/arm, taken from www/firefox52
+
+--- platform/toolkit/components/protobuf/src/google/protobuf/stubs/atomicops.h.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/toolkit/components/protobuf/src/google/protobuf/stubs/atomicops.h
+@@ -76,6 +76,11 @@ typedef intptr_t Atomic64;
+ #endif
+ #endif
+
++#if defined(__NetBSD__) && defined(__arm__)
++// NetBSD/arm uses long for intptr_t, which fails -fpermissive checks. So
++// explicitly use int32 here instead.
++typedef int32 AtomicWord;
++#else
+ // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or
+ // Atomic64 routines below, depending on your architecture.
+ #if defined(__OpenBSD__) && !defined(GOOGLE_PROTOBUF_ARCH_64_BIT)
+@@ -83,6 +88,7 @@ typedef Atomic32 AtomicWord;
+ #else
+ typedef intptr_t AtomicWord;
+ #endif
++#endif
+
+ // Atomically execute:
+ // result = *ptr;
Index: pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h Mon Jul 29 18:13:48 2024
@@ -0,0 +1,91 @@
+$NetBSD: patch-platform_toolkit_components_protobuf_src_google_protobuf_stubs_atomicops__internals__arm__gcc.h,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Fixes for NetBSD/arm, taken from www/firefox52
+
+--- platform/toolkit/components/protobuf/src/google/protobuf/stubs/atomicops_internals_arm_gcc.h.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/toolkit/components/protobuf/src/google/protobuf/stubs/atomicops_internals_arm_gcc.h
+@@ -39,44 +39,19 @@ namespace google {
+ namespace protobuf {
+ namespace internal {
+
+-// 0xffff0fc0 is the hard coded address of a function provided by
+-// the kernel which implements an atomic compare-exchange. On older
+-// ARM architecture revisions (pre-v6) this may be implemented using
+-// a syscall. This address is stable, and in active use (hard coded)
+-// by at least glibc-2.7 and the Android C library.
+-typedef Atomic32 (*LinuxKernelCmpxchgFunc)(Atomic32 old_value,
+- Atomic32 new_value,
+- volatile Atomic32* ptr);
+-LinuxKernelCmpxchgFunc pLinuxKernelCmpxchg __attribute__((weak)) =
+- (LinuxKernelCmpxchgFunc) 0xffff0fc0;
+-
+-typedef void (*LinuxKernelMemoryBarrierFunc)(void);
+-LinuxKernelMemoryBarrierFunc pLinuxKernelMemoryBarrier __attribute__((weak)) =
+- (LinuxKernelMemoryBarrierFunc) 0xffff0fa0;
+-
+-
+ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
+ Atomic32 old_value,
+ Atomic32 new_value) {
+- Atomic32 prev_value = *ptr;
+- do {
+- if (!pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr))) {
+- return old_value;
+- }
+- prev_value = *ptr;
+- } while (prev_value == old_value);
+- return prev_value;
++ return __sync_val_compare_and_swap(ptr, old_value, new_value);
+ }
+
+ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
+ Atomic32 new_value) {
+- Atomic32 old_value;
++ Atomic32 prev_value;
+ do {
+- old_value = *ptr;
+- } while (pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr)));
+- return old_value;
++ prev_value = *ptr;
++ } while (!__sync_bool_compare_and_swap(ptr, prev_value, new_value));
++ return prev_value;
+ }
+
+ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
+@@ -86,17 +61,15 @@ inline Atomic32 NoBarrier_AtomicIncremen
+
+ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
+ Atomic32 increment) {
+- for (;;) {
++ Atomic32 old_value;
++ Atomic32 new_value;
++
++ do {
+ // Atomic exchange the old value with an incremented one.
+- Atomic32 old_value = *ptr;
+- Atomic32 new_value = old_value + increment;
+- if (pLinuxKernelCmpxchg(old_value, new_value,
+- const_cast<Atomic32*>(ptr)) == 0) {
+- // The exchange took place as expected.
+- return new_value;
+- }
+- // Otherwise, *ptr changed mid-loop and we need to retry.
+- }
++ old_value = *ptr;
++ new_value = old_value + increment;
++ } while (!__sync_bool_compare_and_swap(ptr, old_value, new_value));
++ return new_value;
+ }
+
+ inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
+@@ -116,7 +89,7 @@ inline void NoBarrier_Store(volatile Ato
+ }
+
+ inline void MemoryBarrier() {
+- pLinuxKernelMemoryBarrier();
++ __sync_synchronize();
+ }
+
+ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
Index: pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp Mon Jul 29 18:13:48 2024
@@ -0,0 +1,529 @@
+$NetBSD: patch-platform_xpcom_reflect_xptcall_md_unix_xptcinvoke__arm__netbsd.cpp,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Update code to fix NetBSD/arm. Copied from www/firefox52.
+
+--- platform/xpcom/reflect/xptcall/md/unix/xptcinvoke_arm_netbsd.cpp.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/xpcom/reflect/xptcall/md/unix/xptcinvoke_arm_netbsd.cpp
+@@ -7,82 +7,92 @@
+
+ #include "xptcprivate.h"
+
+-// Remember that these 'words' are 32bit DWORDS
++#include "mozilla/Compiler.h"
+
+-static uint32_t
+-invoke_count_words(uint32_t paramCount, nsXPTCVariant* s)
++#ifndef __ARM_PCS_VFP
++
++/* This function copies a 64-bits word from dw to the given pointer in
++ * a buffer delimited by start and end, possibly wrapping around the
++ * buffer boundaries, and/or properly aligning the data at 64-bits word
++ * boundaries (for EABI).
++ * start and end are both assumed to be 64-bits aligned.
++ * Returns a pointer to the second 32-bits word copied (to accomodate
++ * the invoke_copy_to_stack loop).
++ */
++static uint32_t *
++copy_double_word(uint32_t *start, uint32_t *current, uint32_t *end, uint64_t *dw)
+ {
+- uint32_t result = 0;
+- for(uint32_t i = 0; i < paramCount; i++, s++)
+- {
+- if(s->IsPtrData())
+- {
+- result++;
+- continue;
+- }
+- switch(s->type)
+- {
+- case nsXPTType::T_I8 :
+- case nsXPTType::T_I16 :
+- case nsXPTType::T_I32 :
+- result++;
+- break;
+- case nsXPTType::T_I64 :
+- result+=2;
+- break;
+- case nsXPTType::T_U8 :
+- case nsXPTType::T_U16 :
+- case nsXPTType::T_U32 :
+- result++;
+- break;
+- case nsXPTType::T_U64 :
+- result+=2;
+- break;
+- case nsXPTType::T_FLOAT :
+- result++;
+- break;
+- case nsXPTType::T_DOUBLE :
+- result+=2;
+- break;
+- case nsXPTType::T_BOOL :
+- case nsXPTType::T_CHAR :
+- case nsXPTType::T_WCHAR :
+- result++;
+- break;
+- default:
+- // all the others are plain pointer types
+- result++;
+- break;
+- }
++#ifdef __ARM_EABI__
++ /* Aligning the pointer for EABI */
++ current = (uint32_t *)(((uint32_t)current + 7) & ~7);
++ /* Wrap when reaching the end of the buffer */
++ if (current == end) current = start;
++#else
++ /* On non-EABI, 64-bits values are not aligned and when we reach the end
++ * of the buffer, we need to write half of the data at the end, and the
++ * other half at the beginning. */
++ if (current == end - 1) {
++ *current = ((uint32_t*)dw)[0];
++ *start = ((uint32_t*)dw)[1];
++ return start;
+ }
+- return result;
++#endif
++
++ *((uint64_t*) current) = *dw;
++ return current + 1;
+ }
+
+-static void
+-invoke_copy_to_stack(uint32_t* d, uint32_t paramCount, nsXPTCVariant* s)
++/* See stack_space comment in NS_InvokeByIndex to see why this needs not to
++ * be static on DEBUG builds. */
++#ifndef DEBUG
++static
++#endif
++void
++invoke_copy_to_stack(uint32_t* stk, uint32_t *end,
++ uint32_t paramCount, nsXPTCVariant* s)
+ {
++ /* The stack buffer is 64-bits aligned. The end argument points to its end.
++ * The caller is assumed to create a stack buffer of at least four 32-bits
++ * words.
++ * We use the last three 32-bit words to store the values for r1, r2 and r3
++ * for the method call, i.e. the first words for arguments passing.
++ */
++ uint32_t *d = end - 3;
+ for(uint32_t i = 0; i < paramCount; i++, d++, s++)
+ {
++ /* Wrap when reaching the end of the stack buffer */
++ if (d == end) d = stk;
++ NS_ASSERTION(d >= stk && d < end,
++ "invoke_copy_to_stack is copying outside its given buffer");
+ if(s->IsPtrData())
+ {
+ *((void**)d) = s->ptr;
+ continue;
+ }
++ // According to the ARM EABI, integral types that are smaller than a word
++ // are to be sign/zero-extended to a full word and treated as 4-byte values.
++
+ switch(s->type)
+ {
+- case nsXPTType::T_I8 : *((int8_t*) d) = s->val.i8; break;
+- case nsXPTType::T_I16 : *((int16_t*) d) = s->val.i16; break;
++ case nsXPTType::T_I8 : *((int32_t*) d) = s->val.i8; break;
++ case nsXPTType::T_I16 : *((int32_t*) d) = s->val.i16; break;
+ case nsXPTType::T_I32 : *((int32_t*) d) = s->val.i32; break;
+- case nsXPTType::T_I64 : *((int64_t*) d) = s->val.i64; d++; break;
+- case nsXPTType::T_U8 : *((uint8_t*) d) = s->val.u8; break;
+- case nsXPTType::T_U16 : *((uint16_t*)d) = s->val.u16; break;
++ case nsXPTType::T_I64 :
++ d = copy_double_word(stk, d, end, (uint64_t *)&s->val.i64);
++ break;
++ case nsXPTType::T_U8 : *((uint32_t*)d) = s->val.u8; break;
++ case nsXPTType::T_U16 : *((uint32_t*)d) = s->val.u16; break;
+ case nsXPTType::T_U32 : *((uint32_t*)d) = s->val.u32; break;
+- case nsXPTType::T_U64 : *((uint64_t*)d) = s->val.u64; d++; break;
++ case nsXPTType::T_U64 :
++ d = copy_double_word(stk, d, end, (uint64_t *)&s->val.u64);
++ break;
+ case nsXPTType::T_FLOAT : *((float*) d) = s->val.f; break;
+- case nsXPTType::T_DOUBLE : *((double*) d) = s->val.d; d++; break;
+- case nsXPTType::T_BOOL : *((bool*) d) = s->val.b; break;
+- case nsXPTType::T_CHAR : *((char*) d) = s->val.c; break;
+- case nsXPTType::T_WCHAR : *((wchar_t*) d) = s->val.wc; break;
++ case nsXPTType::T_DOUBLE :
++ d = copy_double_word(stk, d, end, (uint64_t *)&s->val.d);
++ break;
++ case nsXPTType::T_BOOL : *((int32_t*) d) = s->val.b; break;
++ case nsXPTType::T_CHAR : *((int32_t*) d) = s->val.c; break;
++ case nsXPTType::T_WCHAR : *((int32_t*) d) = s->val.wc; break;
+ default:
+ // all the others are plain pointer types
+ *((void**)d) = s->val.p;
+@@ -91,47 +101,27 @@ invoke_copy_to_stack(uint32_t* d, uint32
+ }
+ }
+
+-extern "C"
+-struct my_params_struct {
+- nsISupports* that;
+- uint32_t Index;
+- uint32_t Count;
+- nsXPTCVariant* params;
+- uint32_t fn_count;
+- uint32_t fn_copy;
+-};
++typedef nsresult (*vtable_func)(nsISupports *, uint32_t, uint32_t, uint32_t);
+
+-XPTC_PUBLIC_API(nsresult)
+-XPTC_InvokeByIndex(nsISupports* that, uint32_t methodIndex,
++EXPORT_XPCOM_API(nsresult)
++NS_InvokeByIndex(nsISupports* that, uint32_t methodIndex,
+ uint32_t paramCount, nsXPTCVariant* params)
+ {
+- uint32_t result;
+- struct my_params_struct my_params;
+- my_params.that = that;
+- my_params.Index = methodIndex;
+- my_params.Count = paramCount;
+- my_params.params = params;
+- my_params.fn_copy = (uint32_t) &invoke_copy_to_stack;
+- my_params.fn_count = (uint32_t) &invoke_count_words;
+
+ /* This is to call a given method of class that.
+ * The parameters are in params, the number is in paramCount.
+ * The routine will issue calls to count the number of words
+ * required for argument passing and to copy the arguments to
+ * the stack.
+- * Since APCS passes the first 3 params in r1-r3, we need to
+- * load the first three words from the stack and correct the stack
+- * pointer (sp) in the appropriate way. This means:
+- *
+- * 1.) more than 3 arguments: load r1-r3, correct sp and remember No.
+- * of bytes left on the stack in r4
+- *
+- * 2.) <= 2 args: load r1-r3 (we won't be causing a stack overflow I hope),
+- * restore sp as if nothing had happened and set the marker r4 to zero.
+- *
+- * Afterwards sp will be restored using the value in r4 (which is not a temporary register
+- * and will be preserved by the function/method called according to APCS [ARM Procedure
+- * Calling Standard]).
++ * ACPS passes the first 3 params in r1-r3 (with exceptions for 64-bits
++ * arguments), and the remaining goes onto the stack.
++ * We allocate a buffer on the stack for a "worst case" estimate of how much
++ * stack might be needed for EABI, i.e. twice the number of parameters.
++ * The end of this buffer will be used to store r1 to r3, so that the start
++ * of the stack is the remaining parameters.
++ * The magic here is to call the method with "that" and three 32-bits
++ * arguments corresponding to r1-r3, so that the compiler generates the
++ * proper function call. The stack will also contain the remaining arguments.
+ *
+ * !!! IMPORTANT !!!
+ * This routine makes assumptions about the vtable layout of the c++ compiler. It's implemented
+@@ -139,43 +129,272 @@ XPTC_InvokeByIndex(nsISupports* that, ui
+ *
+ */
+
+- __asm__ __volatile__(
+- "ldr r1, [%1, #12] \n\t" /* prepare to call invoke_count_words */
+- "ldr ip, [%1, #16] \n\t" /* r0=paramCount, r1=params */
+- "ldr r0, [%1, #8] \n\t"
+- "mov lr, pc \n\t" /* call it... */
+- "mov pc, ip \n\t"
+- "mov r4, r0, lsl #2 \n\t" /* This is the amount of bytes needed. */
+- "sub sp, sp, r4 \n\t" /* use stack space for the args... */
+- "mov r0, sp \n\t" /* prepare a pointer an the stack */
+- "ldr r1, [%1, #8] \n\t" /* =paramCount */
+- "ldr r2, [%1, #12] \n\t" /* =params */
+- "ldr ip, [%1, #20] \n\t" /* =invoke_copy_to_stack */
+- "mov lr, pc \n\t" /* copy args to the stack like the */
+- "mov pc, ip \n\t" /* compiler would. */
+- "ldr r0, [%1] \n\t" /* =that */
+- "ldr r1, [r0, #0] \n\t" /* get that->vtable offset */
+- "ldr r2, [%1, #4] \n\t"
+- "add r2, r1, r2, lsl #3\n\t" /* a vtable_entry(x)=8 + (8 bytes * x) */
+- "add r2, r2, #8 \n\t" /* with this compilers */
+- "ldr r3, [r2] \n\t" /* get virtual offset from vtable */
+- "mov r3, r3, lsl #16 \n\t"
+- "add r0, r0, r3, asr #16\n\t"
+- "ldr ip, [r2, #4] \n\t" /* get method address from vtable */
+- "cmp r4, #12 \n\t" /* more than 3 arguments??? */
+- "ldmgtia sp!, {r1, r2, r3}\n\t" /* yes: load arguments for r1-r3 */
+- "subgt r4, r4, #12 \n\t" /* and correct the stack pointer */
+- "ldmleia sp, {r1, r2, r3}\n\t" /* no: load r1-r3 from stack */
+- "addle sp, sp, r4 \n\t" /* and restore stack pointer */
+- "movle r4, #0 \n\t" /* a mark for restoring sp */
+- "mov lr, pc \n\t" /* call mathod */
+- "mov pc, ip \n\t"
+- "add sp, sp, r4 \n\t" /* restore stack pointer */
+- "mov %0, r0 \n\t" /* the result... */
+- : "=r" (result)
+- : "r" (&my_params)
+- : "r0", "r1", "r2", "r3", "r4", "ip", "lr"
+- );
+-
+- return result;
++ vtable_func *vtable, func;
++ int base_size = (paramCount > 1) ? paramCount : 2;
++
++/* !!! IMPORTANT !!!
++ * On DEBUG builds, the NS_ASSERTION used in invoke_copy_to_stack needs to use
++ * the stack to pass the 5th argument to NS_DebugBreak. When invoke_copy_to_stack
++ * is inlined, this can result, depending on the compiler and flags, in the
++ * stack pointer not pointing at stack_space when the method is called at the
++ * end of this function. More generally, any function call requiring stack
++ * allocation of arguments is unsafe to be inlined in this function.
++ */
++ uint32_t *stack_space = (uint32_t *) __builtin_alloca(base_size * 8);
++
++ invoke_copy_to_stack(stack_space, &stack_space[base_size * 2],
++ paramCount, params);
++
++ vtable = *reinterpret_cast<vtable_func **>(that);
++ func = vtable[methodIndex];
++
++ return func(that, stack_space[base_size * 2 - 3],
++ stack_space[base_size * 2 - 2],
++ stack_space[base_size * 2 - 1]);
+ }
++
++#else /* __ARM_PCS_VFP */
++
++/* "Procedure Call Standard for the ARM Architecture" document, sections
++ * "5.5 Parameter Passing" and "6.1.2 Procedure Calling" contain all the
++ * needed information.
++ *
++ * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf
++ */
++
++#if defined(__thumb__) && !defined(__thumb2__)
++#error "Thumb1 is not supported"
++#endif
++
++#ifndef __ARMEL__
++#error "Only little endian compatibility was tested"
++#endif
++
++/*
++ * Allocation of integer function arguments initially to registers r1-r3
++ * and then to stack. Handling of 'this' argument which goes to r0 registers
++ * is handled separately and does not belong to these two inline functions.
++ *
++ * The doubleword arguments are allocated to even:odd
++ * register pairs or get aligned at 8-byte boundary on stack. The "holes"
++ * which may appear as a result of this realignment remain unused.
++ *
++ * 'ireg_args' - pointer to the current position in the buffer,
++ * corresponding to the register arguments
++ * 'stack_args' - pointer to the current position in the buffer,
++ * corresponding to the arguments on stack
++ * 'end' - pointer to the end of the registers argument
++ * buffer (it is guaranteed to be 8-bytes aligned)
++ */
++
++static inline void copy_word(uint32_t* &ireg_args,
++ uint32_t* &stack_args,
++ uint32_t* end,
++ uint32_t data)
++{
++ if (ireg_args < end) {
++ *ireg_args = data;
++ ireg_args++;
++ } else {
++ *stack_args = data;
++ stack_args++;
++ }
++}
++
++static inline void copy_dword(uint32_t* &ireg_args,
++ uint32_t* &stack_args,
++ uint32_t* end,
++ uint64_t data)
++{
++ if (ireg_args + 1 < end) {
++ if ((uint32_t)ireg_args & 4) {
++ ireg_args++;
++ }
++ *(uint64_t *)ireg_args = data;
++ ireg_args += 2;
++ } else {
++ if ((uint32_t)stack_args & 4) {
++ stack_args++;
++ }
++ *(uint64_t *)stack_args = data;
++ stack_args += 2;
++ }
++}
++
++/*
++ * Allocation of floating point arguments to VFP registers (s0-s15, d0-d7).
++ *
++ * Unlike integer registers allocation, "back-filling" needs to be
++ * supported. For example, the third floating point argument in the
++ * following function is going to be allocated to s1 register, back-filling
++ * the "hole":
++ * void f(float s0, double d1, float s1)
++ *
++ * Refer to the "Procedure Call Standard for the ARM Architecture" document
++ * for more details.
++ *
++ * 'vfp_s_args' - pointer to the current position in the buffer with
++ * the next unallocated single precision register
++ * 'vfp_d_args' - pointer to the current position in the buffer with
++ * the next unallocated double precision register,
++ * it has the same value as 'vfp_s_args' when back-filling
++ * is not used
++ * 'end' - pointer to the end of the vfp registers argument
++ * buffer (it is guaranteed to be 8-bytes aligned)
++ *
++ * Mozilla bugtracker has a test program attached which be used for
++ * experimenting with VFP registers allocation code and testing its
++ * correctness:
++ * https://bugzilla.mozilla.org/show_bug.cgi?id=601914#c19
++ */
++
++static inline bool copy_vfp_single(float* &vfp_s_args, double* &vfp_d_args,
++ float* end, float data)
++{
++ if (vfp_s_args >= end)
++ return false;
++
++ *vfp_s_args = data;
++ vfp_s_args++;
++ if (vfp_s_args < (float *)vfp_d_args) {
++ // It was the case of back-filling, now the next free single precision
++ // register should overlap with the next free double precision register
++ vfp_s_args = (float *)vfp_d_args;
++ } else if (vfp_s_args > (float *)vfp_d_args) {
++ // also update the pointer to the next free double precision register
++ vfp_d_args++;
++ }
++ return true;
++}
++
++static inline bool copy_vfp_double(float* &vfp_s_args, double* &vfp_d_args,
++ float* end, double data)
++{
++ if (vfp_d_args >= (double *)end) {
++ // The back-filling continues only so long as no VFP CPRC has been
++ // allocated to a slot on the stack. Basically no VFP registers can
++ // be allocated after this point.
++ vfp_s_args = end;
++ return false;
++ }
++
++ if (vfp_s_args == (float *)vfp_d_args) {
++ // also update the pointer to the next free single precision register
++ vfp_s_args += 2;
++ }
++ *vfp_d_args = data;
++ vfp_d_args++;
++ return true;
++}
++
++static void
++invoke_copy_to_stack(uint32_t* stk, uint32_t *end,
++ uint32_t paramCount, nsXPTCVariant* s)
++{
++ uint32_t *ireg_args = end - 3;
++ float *vfp_s_args = (float *)end;
++ double *vfp_d_args = (double *)end;
++ float *vfp_end = vfp_s_args + 16;
++
++ for (uint32_t i = 0; i < paramCount; i++, s++) {
++ if (s->IsPtrData()) {
++ copy_word(ireg_args, stk, end, (uint32_t)s->ptr);
++ continue;
++ }
++ // According to the ARM EABI, integral types that are smaller than a word
++ // are to be sign/zero-extended to a full word and treated as 4-byte values
++ switch (s->type)
++ {
++ case nsXPTType::T_FLOAT:
++ if (!copy_vfp_single(vfp_s_args, vfp_d_args, vfp_end, s->val.f)) {
++ copy_word(end, stk, end, reinterpret_cast<uint32_t&>(s->val.f));
++ }
++ break;
++ case nsXPTType::T_DOUBLE:
++ if (!copy_vfp_double(vfp_s_args, vfp_d_args, vfp_end, s->val.d)) {
++ copy_dword(end, stk, end, reinterpret_cast<uint64_t&>(s->val.d));
++ }
++ break;
++ case nsXPTType::T_I8: copy_word(ireg_args, stk, end, s->val.i8); break;
++ case nsXPTType::T_I16: copy_word(ireg_args, stk, end, s->val.i16); break;
++ case nsXPTType::T_I32: copy_word(ireg_args, stk, end, s->val.i32); break;
++ case nsXPTType::T_I64: copy_dword(ireg_args, stk, end, s->val.i64); break;
++ case nsXPTType::T_U8: copy_word(ireg_args, stk, end, s->val.u8); break;
++ case nsXPTType::T_U16: copy_word(ireg_args, stk, end, s->val.u16); break;
++ case nsXPTType::T_U32: copy_word(ireg_args, stk, end, s->val.u32); break;
++ case nsXPTType::T_U64: copy_dword(ireg_args, stk, end, s->val.u64); break;
++ case nsXPTType::T_BOOL: copy_word(ireg_args, stk, end, s->val.b); break;
++ case nsXPTType::T_CHAR: copy_word(ireg_args, stk, end, s->val.c); break;
++ case nsXPTType::T_WCHAR: copy_word(ireg_args, stk, end, s->val.wc); break;
++ default:
++ // all the others are plain pointer types
++ copy_word(ireg_args, stk, end, reinterpret_cast<uint32_t>(s->val.p));
++ break;
++ }
++ }
++}
++
++typedef uint32_t (*vtable_func)(nsISupports *, uint32_t, uint32_t, uint32_t);
++
++EXPORT_XPCOM_API(nsresult)
++NS_InvokeByIndex(nsISupports* that, uint32_t methodIndex,
++ uint32_t paramCount, nsXPTCVariant* params)
++{
++ vtable_func *vtable = *reinterpret_cast<vtable_func **>(that);
++ vtable_func func = vtable[methodIndex];
++ // 'register uint32_t result asm("r0")' could be used here, but it does not
++ // seem to be reliable in all cases: http://gcc.gnu.org/PR46164
++ nsresult result;
++ asm (
++ "mov r3, sp\n"
++ "mov %[stack_space_size], %[param_count_plus_2], lsl #3\n"
++ "tst r3, #4\n" /* check stack alignment */
++
++ "add %[stack_space_size], #(4 * 16)\n" /* space for VFP registers */
++ "mov r3, %[params]\n"
++
++ "it ne\n"
++ "addne %[stack_space_size], %[stack_space_size], #4\n"
++ "sub r0, sp, %[stack_space_size]\n" /* allocate space on stack */
++
++ "sub r2, %[param_count_plus_2], #2\n"
++ "mov sp, r0\n"
++
++ "add r1, r0, %[param_count_plus_2], lsl #3\n"
++ "blx %[invoke_copy_to_stack]\n"
++
++ "add ip, sp, %[param_count_plus_2], lsl #3\n"
++ "mov r0, %[that]\n"
++ "ldmdb ip, {r1, r2, r3}\n"
++ "vldm ip, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
++ "blx %[func]\n"
++
++ "add sp, sp, %[stack_space_size]\n" /* cleanup stack */
++ "mov %[stack_space_size], r0\n" /* it's actually 'result' variable */
++ : [stack_space_size] "=&r" (result)
++ : [func] "r" (func),
++ [that] "r" (that),
++ [params] "r" (params),
++ [param_count_plus_2] "r" (paramCount + 2),
++ [invoke_copy_to_stack] "r" (invoke_copy_to_stack)
++ : "cc", "memory",
++ // Mark all the scratch registers as clobbered because they may be
++ // modified by the functions, called from this inline assembly block
++ "r0", "r1", "r2", "r3", "ip", "lr",
++ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
++ // Also unconditionally mark d16-d31 registers as clobbered even though
++ // they actually don't exist in vfpv2 and vfpv3-d16 variants. There is
++ // no way to identify VFP variant using preprocessor at the momemnt
++ // (see http://gcc.gnu.org/PR46128 for more details), but fortunately
++ // current versions of gcc do not seem to complain about these registers
++ // even when this code is compiled with '-mfpu=vfpv3-d16' option.
++ // If gcc becomes more strict in the future and/or provides a way to
++ // identify VFP variant, the following d16-d31 registers list needs
++ // to be wrapped into some #ifdef
++ "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
++ "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
++ );
++ return result;
++}
++
++#endif
Index: pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp
diff -u /dev/null pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp:1.1
--- /dev/null Mon Jul 29 18:13:49 2024
+++ pkgsrc/www/palemoon/patches/patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp Mon Jul 29 18:13:48 2024
@@ -0,0 +1,219 @@
+$NetBSD: patch-platform_xpcom_reflect_xptcall_md_unix_xptcstubs__arm__netbsd.cpp,v 1.1 2024/07/29 18:13:48 nia Exp $
+
+Update code to fix NetBSD/arm. Copied from www/firefox52.
+
+--- platform/xpcom/reflect/xptcall/md/unix/xptcstubs_arm_netbsd.cpp.orig 2024-07-10 08:54:53.000000000 +0000
++++ platform/xpcom/reflect/xptcall/md/unix/xptcstubs_arm_netbsd.cpp
+@@ -6,15 +6,32 @@
+ /* Implement shared vtbl methods. */
+
+ #include "xptcprivate.h"
++#include "xptiprivate.h"
+
+-nsresult ATTRIBUTE_USED
++/* Specify explicitly a symbol for this function, don't try to guess the c++ mangled symbol. */
++static nsresult PrepareAndDispatch(nsXPTCStubBase* self, uint32_t methodIndex, uint32_t* args) asm("_PrepareAndDispatch")
++ATTRIBUTE_USED;
++
++#ifdef __ARM_EABI__
++#define DOUBLEWORD_ALIGN(p) ((uint32_t *)((((uint32_t)(p)) + 7) & 0xfffffff8))
++#else
++#define DOUBLEWORD_ALIGN(p) (p)
++#endif
++
++// Apple's iOS toolchain is lame and does not support .cfi directives.
++#ifdef __APPLE__
++#define CFI(str)
++#else
++#define CFI(str) str
++#endif
++
++static nsresult
+ PrepareAndDispatch(nsXPTCStubBase* self, uint32_t methodIndex, uint32_t* args)
+ {
+ #define PARAM_BUFFER_COUNT 16
+
+ nsXPTCMiniVariant paramBuffer[PARAM_BUFFER_COUNT];
+ nsXPTCMiniVariant* dispatchParams = nullptr;
+- nsIInterfaceInfo* iface_info = nullptr;
+ const nsXPTMethodInfo* info;
+ uint8_t paramCount;
+ uint8_t i;
+@@ -22,12 +39,7 @@ PrepareAndDispatch(nsXPTCStubBase* self,
+
+ NS_ASSERTION(self,"no self");
+
+- self->GetInterfaceInfo(&iface_info);
+- NS_ASSERTION(iface_info,"no interface info");
+-
+- iface_info->GetMethodInfo(uint16_t(methodIndex), &info);
+- NS_ASSERTION(info,"no interface info");
+-
++ self->mEntry->GetMethodInfo(uint16_t(methodIndex), &info);
+ paramCount = info->GetParamCount();
+
+ // setup variant array pointer
+@@ -55,13 +67,16 @@ PrepareAndDispatch(nsXPTCStubBase* self,
+ case nsXPTType::T_I8 : dp->val.i8 = *((int8_t*) ap); break;
+ case nsXPTType::T_I16 : dp->val.i16 = *((int16_t*) ap); break;
+ case nsXPTType::T_I32 : dp->val.i32 = *((int32_t*) ap); break;
+- case nsXPTType::T_I64 : dp->val.i64 = *((int64_t*) ap); ap++; break;
++ case nsXPTType::T_I64 : ap = DOUBLEWORD_ALIGN(ap);
++ dp->val.i64 = *((int64_t*) ap); ap++; break;
+ case nsXPTType::T_U8 : dp->val.u8 = *((uint8_t*) ap); break;
+ case nsXPTType::T_U16 : dp->val.u16 = *((uint16_t*)ap); break;
+ case nsXPTType::T_U32 : dp->val.u32 = *((uint32_t*)ap); break;
+- case nsXPTType::T_U64 : dp->val.u64 = *((uint64_t*)ap); ap++; break;
++ case nsXPTType::T_U64 : ap = DOUBLEWORD_ALIGN(ap);
++ dp->val.u64 = *((uint64_t*)ap); ap++; break;
+ case nsXPTType::T_FLOAT : dp->val.f = *((float*) ap); break;
+- case nsXPTType::T_DOUBLE : dp->val.d = *((double*) ap); ap++; break;
++ case nsXPTType::T_DOUBLE : ap = DOUBLEWORD_ALIGN(ap);
++ dp->val.d = *((double*) ap); ap++; break;
+ case nsXPTType::T_BOOL : dp->val.b = *((bool*) ap); break;
+ case nsXPTType::T_CHAR : dp->val.c = *((char*) ap); break;
+ case nsXPTType::T_WCHAR : dp->val.wc = *((wchar_t*) ap); break;
+@@ -71,9 +86,7 @@ PrepareAndDispatch(nsXPTCStubBase* self,
+ }
+ }
+
+- result = self->CallMethod((uint16_t)methodIndex, info, dispatchParams);
+-
+- NS_RELEASE(iface_info);
++ result = self->mOuter->CallMethod((uint16_t)methodIndex, info, dispatchParams);
+
+ if(dispatchParams != paramBuffer)
+ delete [] dispatchParams;
+@@ -82,26 +95,114 @@ PrepareAndDispatch(nsXPTCStubBase* self,
+ }
+
+ /*
+- * These stubs move just move the values passed in registers onto the stack,
+- * so they are contiguous with values passed on the stack, and then calls
+- * PrepareAndDispatch() to do the dirty work.
++ * This is our shared stub.
++ *
++ * r0 = Self.
++ *
++ * The Rules:
++ * We pass an (undefined) number of arguments into this function.
++ * The first 3 C++ arguments are in r1 - r3, the rest are built
++ * by the calling function on the stack.
++ *
++ * We are allowed to corrupt r0 - r3, ip, and lr.
++ *
++ * Other Info:
++ * We pass the stub number in using `ip'.
++ *
++ * Implementation:
++ * - We save r1 to r3 inclusive onto the stack, which will be
++ * immediately below the caller saved arguments.
++ * - setup r2 (PrepareAndDispatch's args pointer) to point at
++ * the base of all these arguments
++ * - Save LR (for the return address)
++ * - Set r1 (PrepareAndDispatch's methodindex argument) from ip
++ * - r0 is passed through (self)
++ * - Call PrepareAndDispatch
++ * - When the call returns, we return by loading the PC off the
++ * stack, and undoing the stack (one instruction)!
++ *
+ */
++__asm__ ("\n"
++ ".text\n"
++ ".align 2\n"
++ "SharedStub:\n"
++ CFI(".cfi_startproc\n")
++ "stmfd sp!, {r1, r2, r3}\n"
++ CFI(".cfi_def_cfa_offset 12\n")
++ CFI(".cfi_offset r3, -4\n")
++ CFI(".cfi_offset r2, -8\n")
++ CFI(".cfi_offset r1, -12\n")
++ "mov r2, sp\n"
++ "str lr, [sp, #-4]!\n"
++ CFI(".cfi_def_cfa_offset 16\n")
++ CFI(".cfi_offset lr, -16\n")
++ "mov r1, ip\n"
++ "bl _PrepareAndDispatch\n"
++ "ldr pc, [sp], #16\n"
++ CFI(".cfi_endproc\n"));
++
++/*
++ * Create sets of stubs to call the SharedStub.
++ * We don't touch the stack here, nor any registers, other than IP.
++ * IP is defined to be corruptable by a called function, so we are
++ * safe to use it.
++ *
++ * This will work with or without optimisation.
++ */
++
++/*
++ * Note : As G++3 ABI contains the length of the functionname in the
++ * mangled name, it is difficult to get a generic assembler mechanism like
++ * in the G++ 2.95 case.
++ * Create names would be like :
++ * _ZN14nsXPTCStubBase5Stub9Ev
++ * _ZN14nsXPTCStubBase6Stub13Ev
++ * _ZN14nsXPTCStubBase7Stub144Ev
++ * Use the assembler directives to get the names right...
++ */
++
++#define STUB_ENTRY(n) \
++ __asm__( \
++ ".section \".text\"\n" \
++" .align 2\n" \
++" .iflt ("#n" - 10)\n" \
++" .globl _ZN14nsXPTCStubBase5Stub"#n"Ev\n" \
++" .type _ZN14nsXPTCStubBase5Stub"#n"Ev,#function\n" \
++"_ZN14nsXPTCStubBase5Stub"#n"Ev:\n" \
++" .else\n" \
++" .iflt ("#n" - 100)\n" \
++" .globl _ZN14nsXPTCStubBase6Stub"#n"Ev\n" \
++" .type _ZN14nsXPTCStubBase6Stub"#n"Ev,#function\n" \
++"_ZN14nsXPTCStubBase6Stub"#n"Ev:\n" \
++" .else\n" \
++" .iflt ("#n" - 1000)\n" \
++" .globl _ZN14nsXPTCStubBase7Stub"#n"Ev\n" \
++" .type _ZN14nsXPTCStubBase7Stub"#n"Ev,#function\n" \
++"_ZN14nsXPTCStubBase7Stub"#n"Ev:\n" \
++" .else\n" \
++" .err \"stub number "#n"> 1000 not yet supported\"\n" \
++" .endif\n" \
++" .endif\n" \
++" .endif\n" \
++" mov ip, #"#n"\n" \
++" b SharedStub\n\t");
++
++#if 0
++/*
++ * This part is left in as comment : this is how the method definition
++ * should look like.
++ */
++
++#define STUB_ENTRY(n) \
++nsresult nsXPTCStubBase::Stub##n () \
++{ \
++ __asm__ ( \
++" mov ip, #"#n"\n" \
++" b SharedStub\n\t"); \
++ return 0; /* avoid warnings */ \
++}
++#endif
+
+-#define STUB_ENTRY(n) \
+-__asm__( \
+- ".global _Stub"#n"__14nsXPTCStubBase\n\t" \
+-"_Stub"#n"__14nsXPTCStubBase:\n\t" \
+- "stmfd sp!, {r1, r2, r3} \n\t" \
+- "mov ip, sp \n\t" \
+- "stmfd sp!, {fp, ip, lr, pc} \n\t" \
+- "sub fp, ip, #4 \n\t" \
+- "mov r1, #"#n" \n\t" /* = methodIndex */ \
+- "add r2, sp, #16 \n\t" \
+- "bl _PrepareAndDispatch__FP14nsXPTCStubBaseUiPUi \n\t" \
+- "ldmea fp, {fp, sp, lr} \n\t" \
+- "add sp, sp, #12 \n\t" \
+- "mov pc, lr \n\t" \
+-);
+
+ #define SENTINEL_ENTRY(n) \
+ nsresult nsXPTCStubBase::Sentinel##n() \
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