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Re: FirePower (was Re: TODO list for ofppc)
root%garbled.net@localhost wrote:
> Here is the procedure to find out the proper io extent:
>
> disable PCI_NETBSD_CONFIGURE and enable PCI_CONF_DUMP. Let the machine boot,
> and for any device that has a sane set of BARs, record where they live. That
> should give you an idea of what the correct io range is. You can test by then
> re-enabling PCI_NETBSD_CONFIGURE, and leaving PCI_CONF_DUMP in.
Hmm, the extent panic happens in the first ofwoea_map_space()
before pci_configure(9) so it fails even without PCI_NETBSD_CONFIGURE
if scells is adjusted. Anyway PCI_CONF_DUMP (with scells=2) shows:
---
pci0 at ofwpci0 bus 0: OFW method configuration space access
pchb0 at pci0 dev 0 function 0: PCI configuration registers:
Common header:
0x00: 0x00371014 0x02000106 0x06000002 0x00000000
Vendor Name: IBM (0x1014)
Device Name: 82660 PowerPC to PCI Bridge and Memory Controller (0x0037)
Command register: 0x0106
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): on
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x02
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x60402000 0x00000000 0x00000000 0x00000000
0x90: 0x7f5f3f1f 0x00000000 0x00000000 0x00000000
0xa0: 0x008a160f 0x00006666 0x00000000 0x00000000
0xb0: 0x00004300 0x00520007 0x4f070000 0x00000000
0xc0: 0x4000002c 0x06000019 0x07e00000 0xe0070000
0xd0: 0x01f801f8 0x0000000d 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
IBM 82660 PowerPC to PCI Bridge and Memory Controller (host bridge, revision
0x02) at ? dev 0 function 0 (intrswiz 0, intrpin 0, i/o off, mem on, no quirks)
pchb0: IBM 82660 PowerPC to PCI Bridge and Memory Controller (rev. 0x02)
pchb0: L1: enabled L2: enabled
pchb0: DRAM EDO (ECC) SRAM sync
pcib0 at pci0 dev 1 function 0: PCI configuration registers:
Common header:
0x00: 0x056510ad 0x02000007 0x06010005 0x00800000
Vendor Name: Symphony Labs (0x10ad)
Device Name: 83C553 PCI-ISA Bridge (0x0565)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: ISA (0x01)
Interface: 0x00
Revision ID: 0x05
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0xef000420 0x0078abfb 0x00000001 0x00443300
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x800001e0 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x0edc0000 0x00000101 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Symphony Labs 83C553 PCI-ISA Bridge (ISA bridge, revision 0x05) at ? dev 1
function 0 (intrswiz 0, intrpin 0, i/o on, mem on, no quirks): Symphony Labs
83C553 PCI-ISA Bridge (rev. 0x05)
pciide0 at pci0 dev 1 function 1: PCI configuration registers:
Common header:
0x00: 0x010510ad 0x02800000 0x01018f05 0x00800008
Vendor Name: Symphony Labs (0x10ad)
Device Name: 82C105 (0x0105)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: IDE (0x01)
Interface: 0x8f
Revision ID: 0x05
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0x000001f1 0x000003f5 0x00000171 0x00000375
0x20: 0x00000001 0x00000001 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x2802010e
Base address register at 0x10
type: 32-bit i/o
base: 0x000001f0, size: 0x00000008
Base address register at 0x14
type: 32-bit i/o
base: 0x000003f4, size: 0x00000004
Base address register at 0x18
type: 32-bit i/o
base: 0x00000170, size: 0x00000008
Base address register at 0x1c
type: 32-bit i/o
base: 0x00000374, size: 0x00000004
Base address register at 0x20
type: 32-bit i/o
base: 0x00000000, size: 0x00000010
Base address register at 0x24
type: 32-bit i/o
base: 0x00000000, size: 0x00000010
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x28
Minimum Grant: 0x02
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0e
Device-dependent header:
0x40: 0x00ff0091 0x00000909 0x00000909 0x00000909
0x50: 0x00000909 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x000000ff
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Symphony Labs 82C105 (IDE mass storage, interface 0x8f, revision 0x05) at ? dev
1 function 1 (intrswiz 0, intrpin 0x1, i/o off, mem off, no quirks)
pciide0: Symphony Labs 82C105 (rev. 0x05)
pciide0: device disabled (at device)
esiop0 at pci0 dev 2 function 0: PCI configuration registers:
Common header:
0x00: 0x00031000 0x02000000 0x01000013 0x00000000
Vendor Name: Symbios Logic (0x1000)
Device Name: 53c825 (0x0003)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: SCSI (0x00)
Interface: 0x00
Revision ID: 0x13
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00001001 0x01820000 0x01821000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x4011010f
Base address register at 0x10
type: 32-bit i/o
base: 0x00001000, size: 0x00000100
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0x01820000, size: 0x00000100
Base address register at 0x18
type: 32-bit nonprefetchable memory
base: 0x01821000, size: 0x00001000
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x40
Minimum Grant: 0x11
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0f
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x330000d6 0x0f000047 0x00000000 0x020f0080
0x90: 0x87fd94d0 0xffffff00 0x3005f000 0x00000000
0xa0: 0x00000000 0x98080000 0x87fd94a0 0x87fd94a0
0xb0: 0x00000000 0x00000000 0x09000000 0x87fd94a0
0xc0: 0x00000000 0x0f60008b 0x0080000d 0x00020007
0xd0: 0x00020000 0x00020000 0x00020000 0x00000000
0xe0: 0x06411489 0xffdd1def 0xb01108dc 0xe954d9fb
0xf0: 0x12855321 0xc5ac5f7c 0x00604563 0x9ceabfb5
Don't know how to pretty-print device-dependent header.
Symbios Logic 53c825 (SCSI mass storage, revision 0x13) at ? dev 2 function 0
(intrswiz 0, intrpin 0x1, i/o off, mem off, no quirks): Symbios Logic 53c825a
(fast wide scsi)
esiop0: unable to map device registers
tlp0 at pci0 dev 4 function 0: PCI configuration registers:
Common header:
0x00: 0x00091011 0x02800006 0x02000022 0x00000000
Vendor Name: Digital Equipment (0x1011)
Device Name: DC21140 ("FasterNet") 10/100 Ethernet (0x0009)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x22
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00001401 0x01822000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00001057
0x30: 0x01040000 0x00000000 0x00000000 0x2814010b
Base address register at 0x10
type: 32-bit i/o
base: 0x00001400, size: 0x00000080
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0x01822000, size: 0x00000080
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1057
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x01040000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x28
Minimum Grant: 0x14
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Device-dependent header:
0x40: 0x0000ee00 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Digital Equipment DC21140 ("FasterNet") 10/100 Ethernet (ethernet network,
revision 0x22) at ? dev 4 function 0 (intrswiz 0, intrpin 0x1, i/o off, mem on,
no quirks): DECchip 21140A Ethernet, pass 2.2
extent_alloc_region: extent `ofwpci mem-space' (0x80000000 - 0x80ffffff)
extent_alloc_region: start 0x1822000, end 0x182207f
panic: extent_alloc_region: region lies outside extent
Stopped in pid 0.1 (system) at netbsd:cpu_Debugger+0x10: lwz r0, r1,
0x14
db>
---
> Yeah.. probably just need to add that compatible id to the code in
> powerpc/pci_machdep_ofw that looks for it.
Treating "PNPpnp,0" as 8259 shows:
---
Symbios Logic 53c825 (SCSI mass storage, revision 0x13) at ? dev 2 function 0
(intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks): Symbios Logic 53c825a
(fast wide scsi)
esiop0: using on-board RAM
esiop0: interrupting at irq 15
trap: pid 0.1 (system): kernel MCHK trap @ 0x1a2904 (SRR1=0x81032)
Press a key to panic.
---
But maybe I guess we should fix pci config.
---
Izumi Tsutsui
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