Re: call for testers - switching ofppc to xorg X11

[Frank Wille <frank%phoenix.owl.de@localhost>]

Michael wrote:

>>  "pcictl list" doesn't show it, either. i'd expect to see it on  
>> pci0, but it isn't:
>>
>> # dmesg|grep 'at pci0'
>> pchb0 at pci0 dev 0 function 0
>> genfb0 at pci0 dev 8 function 0: ATI Technologies Radeon 9200PRO 5960
>> genfb1 at pci0 dev 8 function 1: ATI Technologies Radeon 9200 Pro  
>> Secondary
>> # pcictl pci0 list
>> 000:00:0: Marvell MV6436x System Controller (host bridge, revision  
>> 0x03)
>
> This is weird - if pcictl can't see it then neither can libpciaccess,  
> all it does is walk over /dev/pci* nodes. You can't really blame Xorg  
> for that.

Indeed, that's a bug in ofppc/pci/gt_mainbus.c (it worked with pegasospci
before). The following patch fixes that. I will committ the patch as soon
as kiyohara@, who wrote this file, gives his ok (or doesn't object).

Index: gt_mainbus.c
===================================================================
RCS file: /cvsroot/src/sys/arch/ofppc/pci/gt_mainbus.c,v
retrieving revision 1.2
diff -u -r1.2 gt_mainbus.c
--- gt_mainbus.c    20 Jun 2010 00:25:41 -0000  1.2
+++ gt_mainbus.c    11 Dec 2010 16:30:53 -0000
@@ -49,6 +49,7 @@
 
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pciconf.h>
+#include <dev/pci/pcidevs.h>
 
 #include <dev/marvell/gtreg.h>
 #include <dev/marvell/gtvar.h>
@@ -64,6 +65,9 @@
 #if NGTPCI > 0
 static void gtpci_md_attach_hook(device_t, device_t,
                 struct pcibus_attach_args *);
+static pcireg_t gtpci_agp_conf_read(void *, pcitag_t, int);
+static void gtpci_agp_conf_write(void *, pcitag_t, int, pcireg_t);
+
 void gtpci_md_conf_interrupt(void *, int, int, int, int, int *);
 int gtpci_md_conf_hook(void *, int, int, int, pcireg_t);
 #endif
@@ -122,7 +126,8 @@
 gt_match(device_t parent, cfdata_t cf, void *aux)
 {
    struct confargs *ca = aux;
-   int node, pci, ethernet;
+   uint32_t device_id, vendor_id;
+   int node;
    char name[32];
 
    if (strcmp(ca->ca_name, "gt") != 0 ||
@@ -130,20 +135,27 @@
        return 0;
 
    /* Paranoid check... */
-
-   pci = ethernet = 0;
    for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) {
        memset(name, 0, sizeof(name));
        if (OF_getprop(node, "name", name, sizeof(name)) == -1)
            continue;
-       if (strcmp(name, "pci") == 0)
-           pci++;
-       else if (strcmp(name, "ethernet") == 0)
-           ethernet++;
-
+       if (strcmp(name, "pci") == 0) {
+           for (node = OF_child(node); node;
+               node = OF_peer(node)) {
+               if (OF_getprop(node, "vendor-id",
+                   &vendor_id, sizeof(vendor_id)) == -1)
+                   continue;
+               if (OF_getprop(node, "device-id",
+                   &device_id, sizeof(device_id)) == -1)
+                   continue;
+               /* Find a Marvell system controller */
+               if (vendor_id == PCI_VENDOR_MARVELL &&
+                   device_id == PCI_PRODUCT_MARVELL_MV64360)
+                   return 1;
+           }
+           return 0;
+       }
    }
-   if (pci == 2 && (ethernet == 1 || ethernet == 0))
-       return 1;
    return 0;
 }
 
@@ -243,23 +255,14 @@
        genppc_gtpci0_chipset.pc_bus = busrange[0];
        genppc_gtpci0_chipset.pc_iot = &gtpci0_io_bs_tag;
        genppc_gtpci0_chipset.pc_memt = &gtpci0_mem_bs_tag;
-
-       /* Enable access to space of configuration for AGP. */
-       bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Set,
-           (1 << 23));
+       genppc_gtpci0_chipset.pc_conf_read = gtpci_agp_conf_read;
+       genppc_gtpci0_chipset.pc_conf_write = gtpci_agp_conf_write;
    }
 #endif
 
    gt_attach_common(sc);
-
-#if NGTPCI > 0
-   /* Disable access to space of configuration for AGP. */
-   bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Clear,
-       (1 << 23));
-#endif
 }
 
-
 #if NGTPCI > 0
 static void
 gtpci_md_attach_hook(device_t parent, device_t self,
@@ -304,8 +307,46 @@
        return 0;
    return genofw_pci_conf_hook(sc->sc_pc, bus, dev, func, id);
 }
-#endif
 
+static pcireg_t
+gtpci_agp_conf_read(void *v, pcitag_t tag, int reg)
+{
+   struct gtpci_softc *sc = v;
+   pcireg_t data;
+   int s;
+
+   s = splhigh();
+   /* Enable AGP configuration space access */
+   bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Set, (1 << 23));
+
+   data = gtpci_conf_read(v, tag, reg);
+
+   /* Disable AGP configuration space access */
+   bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Clear,
+       (1 << 23));
+   splx(s);
+
+   return data;
+}
+
+static void
+gtpci_agp_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
+{
+   struct gtpci_softc *sc = v;
+   int s;
+
+   s = splhigh();
+   /* Enable AGP configuration space access */
+   bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Set, (1 << 23));
+
+   gtpci_conf_write(v, tag, reg, data);
+
+   /* Disable AGP configuration space access */
+   bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Clear,
+       (1 << 23));
+   splx(s);
+}
+#endif
 
 void *
 marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)


-- 
Frank Wille