Re: state of riscv?

[Maxime Villard <max%m00nbsd.net@localhost>]

Le 22/07/2020 à 03:01, David Holland a écrit :
> What's the state of the riscv code? Is anyone particularly on top of
> it at this point, since Matt (who wrote it) left?
> 
> And does anyone have major pending changes or can I wade in without
> stepping on anything?

I don't think anybody is working on RISC-V. At least, the two people who said
they would, zmcgrew and me, are not.

Little can be salvaged from Matt's code. The reason being, that it is based on
an ancient draft of the ISA, which does not exactly match the final RISC-V ISA
there exists today.

Off the top of my head, fpu handling is different, exception handling is
different, and several system registers got renamed/replaced (and their bit
fields re-shuffled). There are probably wider differences than that, in
addition.

I had started re-arranging things to abide by the final ISA, but didn't finish.
It was part of a very big diff I had, but it is unlikely I will ever finish it.

As far as I'm concerned, consider you have free hands.

As a hint, I'd say do not hesitate to empty out certain files and rewrite them
from scratch. I realized I was spending too much time trying to figure out how
to repurpose the ancient code, than just rewriting it from scratch with the
final ISA. This left me under the impression that the fastest way forward is
with a flat, from-scratch port.

If it can encourage you, the architecture is rather clean, and the spec is
very easily understandable if we compare against ARMv8 or x86.

Maxime