On Tue, 27 Mar 2007, Martin Husemann wrote:

> Did I understand the processor manual correctly that it is not possible
> to retrieve a cached page of a user context we just evicted from the mmus
> because the cpu will compare the physical address with the PA tag in the
> cache? I.e. if the mmu does not find a valid PA, the cache will not be
> used either?

I don't follow that.

The L1 caches are VIPT which means it uses the virtual address (or 
physical address if using an MMU bypass ASI) to find which cache line to 
examine, but retrieves data from that line if the tag matches the physical 
address of the load.  Since the 16KB cache footprint is twice the 8KB page 
size, you need to make sure the same physical page always has the same 
virtual color.  And since they are write-through, delayed writebacks 
are not an issue.

L2 is PIPT and I/O coherent, so it can be ignored unless you find yourself 
thrashing the cache.


> In that case, at least this blast_dcache() and the one in pmap_remove()
> could be removed, right?

I would think so.  The only time you should have to flush the L1 caches is 
if you need to disable the caching of the page due to a clash in the 
page's virtual color.  Oh, and after DMA completes.

Eduardo