Re: TLB misses on UltraSPARC-IIi

[raymond.meyer%rambler.ru@localhost]

On Wednesday 02 April 2008 18:19:51 Eduardo Horvath wrote:
> Most CISC chips do H/W page table walks.  Most RISC chips don't.  It comes
> down to whether you think the hardware guys or the software guys can lay
> out a more efficient page table.  (Like on Linux all MMUs are Intel
> MMUs...)
>
> Eduardo

How does NetBSD handle it on sparc64, does it have a single TSB, or does it 
have multiple TSBs, i.e. one per process? What are the advantages of single 
vs multiple TSBs?

Does it use larger page sizes to reduce TLB misses, or is it fixed to 8K 
pages?