Re: SMP bugs ( was Re: Severe deadlock issues with 5.0/MP )

[Eduardo Horvath <eeh%NetBSD.org@localhost>]

On Wed, 4 Feb 2009, Michael wrote:

> Also, is what OF reports as 'Watchdog Reset' always an SIR?

There are three different types of resets that may be reported as 
"Watchdog Reset"s depending on the low level reset code on that machine:

Watchog Reset (WDR):            

This is caused when the processor takes too many traps at the same time 
and runs out of its internal trap stack.  sun4u machines usually have a 4 
level trap stack.

Software Initiated Reset (SIR):

This is caused by a sir instruction in the code stream.  I sprinkled it 
throughout locore.s in places that should never be reached.  If you hit an 
SIR then the processor has taken a series of traps in a way the trap 
handling code is unable to recover.  An example would be taking a MMU miss 
while trying to fill a TLB entry from a physically mapped page table.  
Since all addresses in that case should either be wired or physically 
mapped, that condition should never happen unless someone changed the code 
and added a new bug.

Externally Initiated Reset (XIR):

This is an external reset line usually used for debugging.  On most 
desktop machines this terminates in a header on the motherboard to which 
you can attach an external pushbutton.  Some servers have this line 
controlled by a service processor.  JBUS machines (USIIIi) have this 
controlled by the PCI controller in a rather complicated mess.

Eduardo