src: SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 ...

[Repository Conversion <srcmastr%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/71116b6dd9cb
branches:  trunk
changeset: 318012:71116b6dd9cb
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Apr 10 08:18:38 2018 +0000
description:
SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0.

diffstat:

 sys/dev/pci/if_wmreg.h |  6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diffs (20 lines):

diff -r 40786d8ac48f -r 71116b6dd9cb sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Tue Apr 10 07:53:36 2018 +0000
+++ b/sys/dev/pci/if_wmreg.h    Tue Apr 10 08:18:38 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.105 2017/11/22 02:36:52 msaitoh Exp $   */
+/*     $NetBSD: if_wmreg.h,v 1.106 2018/04/10 08:18:38 msaitoh Exp $   */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -590,8 +590,8 @@
 #define        FCAL_CONST      0x00c28001      /* Flow Control MAC addr low */
 
 #define        WMREG_FEXTNVM   0x0028  /* Future Extended NVM register */
-#define        FEXTNVM_SW_CONFIG       __BIT(1)
-#define        FEXTNVM_SW_CONFIG_ICH8M __BIT(27)
+#define        FEXTNVM_SW_CONFIG       __BIT(0)  /* SW PHY Config En (ICH8 B0) */
+#define        FEXTNVM_SW_CONFIG_ICH8M __BIT(27) /* SW PHY Config En (>= ICH8 B1) */
 
 #define        WMREG_FCAH      0x002c  /* Flow Control Address High */
 #define        FCAH_CONST      0x00000100      /* Flow Control MAC addr high */