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src: Add PCH_CNP support (I219 with Intel 300 series chipset).
details: https://anonhg.NetBSD.org/src/rev/862002beccc6
branches: trunk
changeset: 318089:862002beccc6
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Thu Apr 12 03:25:08 2018 +0000
description:
Add PCH_CNP support (I219 with Intel 300 series chipset).
It's required more test, so it's disabled by default.
diffstat:
sys/dev/pci/if_wm.c | 89 ++++++++++++++++++++++++++++++++++++-------------
sys/dev/pci/if_wmvar.h | 5 +-
2 files changed, 68 insertions(+), 26 deletions(-)
diffs (truncated from 416 to 300 lines):
diff -r f134e5cd321d -r 862002beccc6 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Thu Apr 12 03:13:04 2018 +0000
+++ b/sys/dev/pci/if_wm.c Thu Apr 12 03:25:08 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.569 2018/04/12 03:13:04 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.570 2018/04/12 03:25:08 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.569 2018/04/12 03:13:04 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.570 2018/04/12 03:25:08 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -1513,6 +1513,18 @@
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM5,
"I219 LM Ethernet Connection",
WM_T_PCH_SPT, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V6,
+ "I219 V Ethernet Connection",
+ WM_T_PCH_CNP, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V7,
+ "I219 V Ethernet Connection",
+ WM_T_PCH_CNP, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM6,
+ "I219 LM Ethernet Connection",
+ WM_T_PCH_CNP, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM7,
+ "I219 LM Ethernet Connection",
+ WM_T_PCH_CNP, WMP_F_COPPER },
#endif
{ 0, 0,
NULL,
@@ -1986,7 +1998,8 @@
&& (sc->sc_type != WM_T_PCH)
&& (sc->sc_type != WM_T_PCH2)
&& (sc->sc_type != WM_T_PCH_LPT)
- && (sc->sc_type != WM_T_PCH_SPT)) {
+ && (sc->sc_type != WM_T_PCH_SPT)
+ && (sc->sc_type != WM_T_PCH_CNP)) {
/* ICH* and PCH* have no PCIe capability registers */
if (pci_get_capability(pa->pa_pc, pa->pa_tag,
PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
@@ -2233,6 +2246,7 @@
sc->nvm.release = wm_put_nvm_ich8lan;
break;
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
sc->nvm.read = wm_nvm_read_spt;
/* SPT has no GFPREG; flash registers mapped through BAR0 */
sc->sc_flags |= WM_F_EEPROM_FLASH;
@@ -2468,6 +2482,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
/* XXX The funcid should be checked on some devices */
apme_mask = WUC_APME;
eeprom_data = CSR_READ(sc, WMREG_WUC);
@@ -2577,7 +2592,8 @@
if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
|| sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
|| sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
- || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
+ || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_PCH_CNP
+ || sc->sc_type == WM_T_82573
|| sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
/* Copper only */
} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
@@ -2731,6 +2747,7 @@
case WM_T_PCH2: /* PCH2 supports 9K frame size */
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
/* XXX limited to 9234 */
sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
break;
@@ -3374,6 +3391,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
if (idx == 0) {
CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
CSR_WRITE_FLUSH(sc);
@@ -3431,7 +3449,7 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
|| (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT)) {
+ || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
(((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
return (hash & 0x3ff);
@@ -3486,7 +3504,8 @@
size = WM_RAL_TABSIZE_ICH8;
else if (sc->sc_type == WM_T_PCH2)
size = WM_RAL_TABSIZE_PCH2;
- else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
+ else if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+ || (sc->sc_type == WM_T_PCH_CNP))
size = WM_RAL_TABSIZE_PCH_LPT;
else if (sc->sc_type == WM_T_82575)
size = WM_RAL_TABSIZE_82575;
@@ -3498,7 +3517,8 @@
size = WM_RAL_TABSIZE;
wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
- if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
+ if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+ || (sc->sc_type == WM_T_PCH_CNP)) {
i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
switch (i) {
case 0:
@@ -3523,7 +3543,7 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
|| (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT))
+ || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP))
size = WM_ICH8_MC_TABSIZE;
else
size = WM_MC_TABSIZE;
@@ -3556,7 +3576,8 @@
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
|| (sc->sc_type == WM_T_PCH2)
|| (sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT))
+ || (sc->sc_type == WM_T_PCH_SPT)
+ || (sc->sc_type == WM_T_PCH_CNP))
reg &= 0x1f;
else
reg &= 0x7f;
@@ -3698,6 +3719,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
reg = CSR_READ(sc, WMREG_STATUS);
if ((reg & STATUS_LAN_INIT_DONE) != 0)
@@ -3784,6 +3806,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
delay(10*1000);
if (sc->sc_type >= WM_T_ICH10)
wm_lan_init_done(sc);
@@ -3903,6 +3926,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
break;
default:
@@ -4115,6 +4139,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
/* TARC0 */
if (sc->sc_type == WM_T_ICH8) {
/* Set TARC0 bits 29 and 28 */
@@ -4422,9 +4447,10 @@
PBA_14K : PBA_10K;
break;
case WM_T_PCH:
- case WM_T_PCH2:
+ case WM_T_PCH2: /* XXX 14K? */
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
sc->sc_pba = PBA_26K;
break;
default:
@@ -4549,6 +4575,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
if (wm_phy_resetisblocked(sc) == false) {
/*
@@ -4680,6 +4707,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
break;
default:
panic("%s: unknown type\n", __func__);
@@ -4728,7 +4756,7 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
|| (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT)) {
+ || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
reg = CSR_READ(sc, WMREG_KABGTXD);
reg |= KABGTXD_BGSQLBIAS;
CSR_WRITE(sc, WMREG_KABGTXD, reg);
@@ -5411,7 +5439,7 @@
if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
wm_get_hw_control(sc);
- if ((sc->sc_type == WM_T_PCH_SPT) &&
+ if ((sc->sc_type >= WM_T_PCH_SPT) &&
pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
wm_legacy_irq_quirk_spt(sc);
@@ -5482,7 +5510,7 @@
if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
&& (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
&& (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
- && (sc->sc_type != WM_T_PCH_SPT)) {
+ && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)){
CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
@@ -5517,6 +5545,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
/*
* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when
@@ -5853,6 +5882,7 @@
break;
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
reg = CSR_READ(sc, WMREG_PBECCSTS);
reg |= PBECCSTS_UNCORR_ECC_ENABLE;
CSR_WRITE(sc, WMREG_PBECCSTS, reg);
@@ -8659,8 +8689,7 @@
* on power up.
* Set the Beacon Duration for I217 to 8 usec
*/
- if ((sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT)) {
+ if (sc->sc_type >= WM_T_PCH_LPT) {
reg = CSR_READ(sc, WMREG_FEXTNVM4);
reg &= ~FEXTNVM4_BEACON_DURATION;
reg |= FEXTNVM4_BEACON_DURATION_8US;
@@ -8670,8 +8699,7 @@
/* XXX Work-around I218 hang issue */
/* e1000_k1_workaround_lpt_lp() */
- if ((sc->sc_type == WM_T_PCH_LPT)
- || (sc->sc_type == WM_T_PCH_SPT)) {
+ if (sc->sc_type >= WM_T_PCH_LPT) {
/*
* Set platform power management values for Latency
* Tolerance Reporting (LTR)
@@ -9276,6 +9304,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
/* generic reset */
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
CSR_WRITE_FLUSH(sc);
@@ -9334,6 +9363,7 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
+ case WM_T_PCH_CNP:
wm_phy_post_reset(sc);
break;
default:
@@ -9560,7 +9590,7 @@
new_readreg = wm_gmii_bm_readreg;
new_writereg = wm_gmii_bm_writereg;
}
- if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) {
+ if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_CNP)) {
/* All PCH* use _hv_ */
new_readreg = wm_gmii_hv_readreg;
new_writereg = wm_gmii_hv_writereg;
@@ -9678,7 +9708,8 @@
/* get PHY control from SMBus to PCIe */
if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
- || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT))
+ || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+ || (sc->sc_type == WM_T_PCH_CNP))
wm_smbustopci(sc);
wm_gmii_reset(sc);
@@ -9732,8 +9763,10 @@
* If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
* wm_set_mdio_slow_mode_hv() for a workaround and retry.
*/
- if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
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