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[src/trunk]: src/sys/arch/arm/allwinner Work-in-progress support for the AllW...
details: https://anonhg.NetBSD.org/src/rev/556dabf93ae7
branches: trunk
changeset: 332810:556dabf93ae7
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Oct 10 07:36:11 2014 +0000
description:
Work-in-progress support for the AllWinner A31 SoC.
diffstat:
sys/arch/arm/allwinner/awin_board.c | 73 ++++++++++++++++++++++-------
sys/arch/arm/allwinner/awin_intr.h | 19 +++++++-
sys/arch/arm/allwinner/awin_io.c | 48 +++++++++++--------
sys/arch/arm/allwinner/awin_mmc.c | 74 +++++++++++++++++++++++-------
sys/arch/arm/allwinner/awin_reg.h | 50 ++++++++++++++++++++-
sys/arch/arm/allwinner/awin_usb.c | 88 +++++++++++++++++++++++++++++-------
sys/arch/arm/allwinner/awin_wdt.c | 18 +++++-
7 files changed, 288 insertions(+), 82 deletions(-)
diffs (truncated from 643 to 300 lines):
diff -r cfee41d2141b -r 556dabf93ae7 sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c Fri Oct 10 07:08:26 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c Fri Oct 10 07:36:11 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.20 2014/10/04 19:38:17 martin Exp $ */
+/* $NetBSD: awin_board.c,v 1.21 2014/10/10 07:36:11 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.20 2014/10/04 19:38:17 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.21 2014/10/10 07:36:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -123,8 +123,11 @@
awin_cpu_clk(void)
{
struct cpu_info * const ci = curcpu();
+ u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 ?
+ AWIN_A31_CPU_AXI_CFG_REG :
+ AWIN_CPU_AHB_APB0_CFG_REG;
const uint32_t cpu0_cfg = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
- AWIN_CCM_OFFSET + AWIN_CPU_AHB_APB0_CFG_REG);
+ AWIN_CCM_OFFSET + reg);
const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL);
switch (__SHIFTOUT(cpu_clk_sel, AWIN_CPU_CLK_SRC_SEL)) {
case AWIN_CPU_CLK_SRC_SEL_LOSC:
@@ -136,10 +139,18 @@
case AWIN_CPU_CLK_SRC_SEL_PLL1: {
const uint32_t pll1_cfg = bus_space_read_4(&awin_bs_tag,
awin_core_bsh, AWIN_CCM_OFFSET + AWIN_PLL1_CFG_REG);
- u_int p = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_OUT_EXP_DIVP);
- u_int n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N);
- u_int k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
- u_int m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1;
+ u_int p, n, k, m;
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ p = 0;
+ n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N) + 1;
+ k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
+ m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1;
+ } else {
+ p = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_OUT_EXP_DIVP);
+ n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N);
+ k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
+ m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1;
+ }
ci->ci_data.cpu_cc_freq =
((uint64_t)AWIN_REF_FREQ * (n ? n : 1) * k / m) >> p;
break;
@@ -185,11 +196,24 @@
#endif
#ifdef VERBOSE_INIT_ARM
- uint32_t s0 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
- AWIN_CPUCFG_OFFSET + AWIN_CPUCFG_CPU0_STATUS_REG);
- uint32_t s1 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
- AWIN_CPUCFG_OFFSET + AWIN_CPUCFG_CPU1_STATUS_REG);
- printf("%s: cpu status: 0=%#x 1=%#x\n", __func__, s0, s1);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ uint32_t s0 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU0_STATUS_REG);
+ uint32_t s1 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU1_STATUS_REG);
+ uint32_t s2 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU2_STATUS_REG);
+ uint32_t s3 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU3_STATUS_REG);
+ printf("%s: cpu status: 0=%#x 1=%#x 2=%#x 3=%#x\n", __func__,
+ s0, s1, s2, s3);
+ } else {
+ uint32_t s0 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_CPUCFG_OFFSET + AWIN_CPUCFG_CPU0_STATUS_REG);
+ uint32_t s1 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+ AWIN_CPUCFG_OFFSET + AWIN_CPUCFG_CPU1_STATUS_REG);
+ printf("%s: cpu status: 0=%#x 1=%#x\n", __func__, s0, s1);
+ }
#endif
#if !defined(MULTIPROCESSOR) && defined(VERBOSE_INIT_ARM)
@@ -228,16 +252,27 @@
psize_t
awin_memprobe(void)
{
- const uint32_t dcr = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
- AWIN_DRAM_OFFSET + AWIN_DRAM_DCR_REG);
+ psize_t memsize;
- psize_t memsize = (__SHIFTOUT(dcr, AWIN_DRAM_DCR_BUS_WIDTH) + 1)
- / __SHIFTOUT(dcr, AWIN_DRAM_DCR_IO_WIDTH);
- memsize *= 1 << (__SHIFTOUT(dcr, AWIN_DRAM_DCR_CHIP_DENSITY) + 28 - 3);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
#ifdef VERBOSE_INIT_ARM
- printf("sdram_config = %#x, memsize = %uMB\n", dcr,
- (u_int)(memsize >> 20));
+ printf("memprobe not supported on A31\n");
#endif
+ memsize = 0;
+ } else {
+ const uint32_t dcr = bus_space_read_4(&awin_bs_tag,
+ awin_core_bsh,
+ AWIN_DRAM_OFFSET + AWIN_DRAM_DCR_REG);
+
+ memsize = (__SHIFTOUT(dcr, AWIN_DRAM_DCR_BUS_WIDTH) + 1)
+ / __SHIFTOUT(dcr, AWIN_DRAM_DCR_IO_WIDTH);
+ memsize *= 1 << (__SHIFTOUT(dcr, AWIN_DRAM_DCR_CHIP_DENSITY)
+ + 28 - 3);
+#ifdef VERBOSE_INIT_ARM
+ printf("sdram_config = %#x, memsize = %uMB\n", dcr,
+ (u_int)(memsize >> 20));
+#endif
+ }
return memsize;
}
diff -r cfee41d2141b -r 556dabf93ae7 sys/arch/arm/allwinner/awin_intr.h
--- a/sys/arch/arm/allwinner/awin_intr.h Fri Oct 10 07:08:26 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_intr.h Fri Oct 10 07:36:11 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_intr.h,v 1.4 2014/09/03 21:42:46 jmcneill Exp $ */
+/* $NetBSD: awin_intr.h,v 1.5 2014/10/10 07:36:11 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -134,4 +134,21 @@
#define AWIN_IRQ_TWI4 121
#define AWIN_IRQ_IIS2 122
+/*
+ * A31
+ */
+#define AWIN_A31_IRQ_UART0 32
+#define AWIN_A31_IRQ_AC 61
+#define AWIN_A31_IRQ_DMA 82
+#define AWIN_A31_IRQ_SDMMC0 92
+#define AWIN_A31_IRQ_SDMMC1 93
+#define AWIN_A31_IRQ_SDMMC2 94
+#define AWIN_A31_IRQ_SDMMC3 95
+#define AWIN_A31_IRQ_USB0 103
+#define AWIN_A31_IRQ_USB1 104
+#define AWIN_A31_IRQ_USB2 105
+#define AWIN_A31_IRQ_USB3 106
+#define AWIN_A31_IRQ_USB4 108
+#define AWIN_A31_IRQ_GMAC 114
+
#endif /* _ARM_ALLWINNER_AWIN_INTR_H_ */
diff -r cfee41d2141b -r 556dabf93ae7 sys/arch/arm/allwinner/awin_io.c
--- a/sys/arch/arm/allwinner/awin_io.c Fri Oct 10 07:08:26 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_io.c Fri Oct 10 07:36:11 2014 +0000
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.15 2014/09/11 02:21:19 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.16 2014/10/10 07:36:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -94,27 +94,33 @@
static const struct awin_locators awin_locators[] = {
{ "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ },
{ "awingpio", OFFANDSIZE(PIO), NOPORT, NOINTR, AANY|REQ },
- { "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_IRQ_DMA, AANY|REQ },
+ { "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_IRQ_DMA, A10|A20|REQ },
+ { "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_A31_IRQ_DMA, A31|REQ },
{ "awintmr", OFFANDSIZE(TMR), NOPORT, AWIN_IRQ_TMR0, A10 },
- { "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, AANY },
- { "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, AANY },
- { "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, AANY },
- { "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, AANY },
- { "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, AANY },
- { "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, AANY },
- { "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, AANY },
- { "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, AANY },
+ { "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, A10|A20 },
+ { "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, A10|A20 },
+ { "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, A10|A20 },
+ { "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, A10|A20 },
+ { "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, A10|A20 },
+ { "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, A10|A20 },
+ { "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, A10|A20 },
+ { "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, A10|A20 },
+ { "com", OFFANDSIZE(UART0), 0, AWIN_A31_IRQ_UART0, A31 },
{ "awinwdt", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY },
{ "awinrtc", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY },
{ "awinhdmi", OFFANDSIZE(HDMI), NOPORT, AWIN_IRQ_HDMI0, A20 },
- { "awinusb", OFFANDSIZE(USB1), 0, NOINTR, AANY },
- { "awinusb", OFFANDSIZE(USB2), 1, NOINTR, AANY },
- { "motg", OFFANDSIZE(USB0), NOPORT, AWIN_IRQ_USB0, AANY },
- { "awinmmc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, AANY },
- { "awinmmc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, AANY },
- { "awinmmc", OFFANDSIZE(SDMMC2), 2, AWIN_IRQ_SDMMC2, AANY },
- { "awinmmc", OFFANDSIZE(SDMMC3), 3, AWIN_IRQ_SDMMC3, AANY },
- { "awinmmc", OFFANDSIZE(SDMMC1), 4, AWIN_IRQ_SDMMC1, AANY },
+ { "awinusb", OFFANDSIZE(USB1), 0, NOINTR, A10|A20 },
+ { "awinusb", OFFANDSIZE(USB2), 1, NOINTR, A10|A20 },
+ { "awinusb", OFFANDSIZE(A31_USB1), 0, NOINTR, A31 },
+ { "awinusb", OFFANDSIZE(A31_USB2), 1, NOINTR, A31 },
+ { "motg", OFFANDSIZE(USB0), NOPORT, AWIN_IRQ_USB0, A10|A20 },
+ { "motg", OFFANDSIZE(A31_USB0), NOPORT, AWIN_A31_IRQ_USB0, A31 },
+ { "awinmmc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, A10|A20 },
+ { "awinmmc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, A10|A20 },
+ { "awinmmc", OFFANDSIZE(SDMMC2), 2, AWIN_IRQ_SDMMC2, A10|A20 },
+ { "awinmmc", OFFANDSIZE(SDMMC3), 3, AWIN_IRQ_SDMMC3, A10|A20 },
+ { "awinmmc", OFFANDSIZE(SDMMC1), 4, AWIN_IRQ_SDMMC1, A10|A20 },
+ { "awinmmc", OFFANDSIZE(SDMMC0), 0, AWIN_A31_IRQ_SDMMC0, A31 },
{ "ahcisata", OFFANDSIZE(SATA), NOPORT, AWIN_IRQ_SATA, AANY },
{ "awiniic", OFFANDSIZE(TWI0), 0, AWIN_IRQ_TWI0, AANY },
{ "awiniic", OFFANDSIZE(TWI1), 1, AWIN_IRQ_TWI1, AANY },
@@ -126,9 +132,11 @@
{ "spi", OFFANDSIZE(SPI2), 1, AWIN_IRQ_SPI2, AANY },
{ "spi", OFFANDSIZE(SPI3), 3, AWIN_IRQ_SPI3, AANY },
{ "awe", OFFANDSIZE(EMAC), NOPORT, AWIN_IRQ_EMAC, AANY },
- { "awge", OFFANDSIZE(GMAC), NOPORT, AWIN_IRQ_GMAC, A20|A31 },
+ { "awge", OFFANDSIZE(GMAC), NOPORT, AWIN_IRQ_GMAC, A20 },
+ { "awge", OFFANDSIZE(GMAC), NOPORT, AWIN_A31_IRQ_GMAC, A31 },
{ "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY },
- { "awinac", OFFANDSIZE(AC), NOPORT, AWIN_IRQ_AC, AANY },
+ { "awinac", OFFANDSIZE(AC), NOPORT, AWIN_IRQ_AC, A10|A20 },
+ { "awinac", OFFANDSIZE(AC), NOPORT, AWIN_A31_IRQ_AC, A31 },
};
static int
diff -r cfee41d2141b -r 556dabf93ae7 sys/arch/arm/allwinner/awin_mmc.c
--- a/sys/arch/arm/allwinner/awin_mmc.c Fri Oct 10 07:08:26 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_mmc.c Fri Oct 10 07:36:11 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_mmc.c,v 1.11 2014/10/03 11:23:29 jmcneill Exp $ */
+/* $NetBSD: awin_mmc.c,v 1.12 2014/10/10 07:36:11 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.11 2014/10/03 11:23:29 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.12 2014/10/10 07:36:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -46,7 +46,6 @@
#include <arm/allwinner/awin_var.h>
#define AWIN_MMC_NDESC 16
-#define AWIN_MMC_WATERMARK 0x20070008
static int awin_mmc_match(device_t, cfdata_t, void *);
static void awin_mmc_attach(device_t, device_t, void *);
@@ -105,6 +104,9 @@
unsigned int sc_pll_freq;
unsigned int sc_mod_clk;
+ uint32_t sc_dma_ftrgl;
+ uint32_t sc_fifo_reg;
+
uint32_t sc_idma_xferlen;
bus_dma_segment_t sc_idma_segs[1];
int sc_idma_nsegs;
@@ -158,11 +160,24 @@
val = bus_space_read_4(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_PLL6_CFG_REG);
- n = (val >> 8) & 0x1f;
- k = ((val >> 4) & 3) + 1;
- p = 1 << ((val >> 16) & 3);
-
- freq = 24000000 * n * k / p;
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ n = ((val >> 8) & 0x1f) + 1;
+ k = ((val >> 4) & 3) + 1;
+ freq = 24000000 * n * k / 2;
+#ifdef AWIN_MMC_DEBUG
+ device_printf(sc->sc_dev, "n = %d k = %d freq = %u\n",
+ n, k, freq);
+#endif
+ } else {
+ n = (val >> 8) & 0x1f;
+ k = ((val >> 4) & 3) + 1;
+ p = 1 << ((val >> 16) & 3);
+ freq = 24000000 * n * k / p;
+#ifdef AWIN_MMC_DEBUG
+ device_printf(sc->sc_dev, "n = %d k = %d p = %d freq = %u\n",
+ n, k, p, freq);
+#endif
+ }
sc->sc_pll_freq = freq;
div = ((sc->sc_pll_freq + 99999999) / 100000000) - 1;
@@ -275,6 +290,14 @@
}
}
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ sc->sc_dma_ftrgl = 0x2007000f;
+ sc->sc_fifo_reg = AWIN_A31_MMC_FIFO;
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