[src/trunk]: src/sys/arch/mips/ingenic moar registers

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d8b6f309f999
branches:  trunk
changeset: 336670:d8b6f309f999
user:      macallan <macallan%NetBSD.org@localhost>
date:      Mon Mar 09 13:22:37 2015 +0000

description:
moar registers

diffstat:

 sys/arch/mips/ingenic/ingenic_regs.h |  13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diffs (33 lines):

diff -r 68e9f00b7064 -r d8b6f309f999 sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h      Mon Mar 09 12:32:11 2015 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h      Mon Mar 09 13:22:37 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ingenic_regs.h,v 1.7 2015/03/07 15:36:16 macallan Exp $ */
+/*     $NetBSD: ingenic_regs.h,v 1.8 2015/03/09 13:22:37 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -221,7 +221,7 @@
        #define PCR_TXPREEMPH   0x00000080      /* HS transm. pre-emphasis */
        #define PCR_TXHSXVTUNE1 0x00000060      /* dp/dm voltage adj. */
        #define PCR_TXVREFTUNE1 0x00000017      /* HS DC voltage adj. */
-       #define PCR_TXRISETUNE1 0x00000001      /* risa/fall wave adj. */
+       #define PCR_TXRISETUNE1 0x00000001      /* rise/fall wave adj. */
 
 #define JZ_UHCCDR      0x1000006c      /* UHC Clock Divider Register */
 #define JZ_SPCR0       0x100000b8      /* SRAM Power Control Registers */
@@ -255,5 +255,14 @@
        #define DMMAP_BASE      0x0000ff00      /* base PADDR of memory chunk */
        #define DMMAP_MASK      0x000000ff      /* mask which bits of PADDR are
                                                 * constant */
+/* USB controllers */
+#define JZ_EHCI_BASE   0x13490000
+#define JZ_OHCI_BASE   0x134a0000
+#define JZ_DWC2_BASE   0x13500000
+
+/* Ethernet */
+#define JZ_DME_BASE    0x16000000
+#define JZ_DME_IO      JZ_DME_BASE
+#define JZ_DME_ADDR    (JZ_DME_BASE + 2)
 
 #endif /* INGENIC_REGS_H */