[src/trunk]: src/sys/arch/arm/include Add Revision ID register

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/440ad93c92a7
branches:  trunk
changeset: 338580:440ad93c92a7
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat May 30 20:39:56 2015 +0000

description:
Add Revision ID register

diffstat:

 sys/arch/arm/include/armreg.h |  3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diffs (17 lines):

diff -r 02bf5ff8c67f -r 440ad93c92a7 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Sat May 30 20:09:47 2015 +0000
+++ b/sys/arch/arm/include/armreg.h     Sat May 30 20:39:56 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.105 2015/05/20 02:59:57 hsuenaga Exp $    */
+/*     $NetBSD: armreg.h,v 1.106 2015/05/30 20:39:56 skrll Exp $       */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -900,6 +900,7 @@
 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */
 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
+ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */
 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */