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[src/trunk]: src/sys/dev/tc - I finally learned CSR_A register of IMS G332 VD...
details: https://anonhg.NetBSD.org/src/rev/229db5f3f8fc
branches: trunk
changeset: 472455:229db5f3f8fc
user: nisimura <nisimura%NetBSD.org@localhost>
date: Fri Apr 30 00:44:11 1999 +0000
description:
- I finally learned CSR_A register of IMS G332 VDAC must be treated as
write only. Read-motify-write operation breaks its video mode.
- VDAC regiters are now initialized as ULTRIX does.
diffstat:
sys/dev/tc/xcfb.c | 124 +++++++++++++++++++++++++++++++++++------------------
1 files changed, 81 insertions(+), 43 deletions(-)
diffs (265 lines):
diff -r 463968b3e3f5 -r 229db5f3f8fc sys/dev/tc/xcfb.c
--- a/sys/dev/tc/xcfb.c Thu Apr 29 23:39:55 1999 +0000
+++ b/sys/dev/tc/xcfb.c Fri Apr 30 00:44:11 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: xcfb.c,v 1.8 1999/03/29 07:22:02 nisimura Exp $ */
+/* $NetBSD: xcfb.c,v 1.9 1999/04/30 00:44:11 nisimura Exp $ */
/*
* Copyright (c) 1998 Tohru Nishimura. All rights reserved.
@@ -32,7 +32,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: xcfb.c,v 1.8 1999/03/29 07:22:02 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xcfb.c,v 1.9 1999/04/30 00:44:11 nisimura Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -52,6 +52,7 @@
#include <dev/wscons/wsdisplayvar.h>
#include <dev/tc/tcvar.h>
+#include <dev/tc/ioasicreg.h>
#include <dev/ic/ims332reg.h>
#include <uvm/uvm_extern.h>
@@ -89,9 +90,9 @@
#define XCFB_FB_OFFSET 0x2000000 /* from module's base */
#define XCFB_FB_SIZE 0x100000 /* frame buffer size */
-#define IMS332_ADDRESS 0xbc140000
-#define IMS332_RPTR 0xbc1c0000
-#define IMS332_WPTR 0xbc1e0000
+#define IMS332_HIGH (IOASIC_SLOT_5_START)
+#define IMS332_RLOW (IOASIC_SLOT_7_START)
+#define IMS332_WLOW (IOASIC_SLOT_7_START + 0x20000)
struct xcfb_softc {
struct device sc_dev;
@@ -101,6 +102,7 @@
/* XXX MAXINE can take PMAG-DV virtical retrace interrupt XXX */
int nscreens;
/* cursor coordiate is located at upper-left corner */
+ int sc_csr; /* software copy of IMS332 CSR A */
};
int xcfbmatch __P((struct device *, struct cfdata *, void *));
@@ -114,6 +116,7 @@
struct fb_devconfig xcfb_console_dc;
tc_addr_t xcfb_consaddr;
+
struct wsdisplay_emulops xcfb_emulops = {
rcons_cursor,
rcons_mapchar,
@@ -159,6 +162,7 @@
};
int xcfb_cnattach __P((tc_addr_t));
+int xcfbintr __P((void *));
void xcfbinit __P((struct fb_devconfig *));
void xcfb_screenblank __P((struct xcfb_softc *));
@@ -175,6 +179,8 @@
u_int32_t ims332_read_reg __P((int));
void ims332_write_reg __P((int, u_int32_t));
+extern long ioasic_base; /* XXX */
+
/*
* Compose 2 bit/pixel cursor image.
* M M M M I I I I M I M I M I M I
@@ -285,8 +291,13 @@
struct xcfb_softc *sc = (struct xcfb_softc *)self;
struct tc_attach_args *ta = aux;
struct wsemuldisplaydev_attach_args waa;
+#if 1
+ struct hwcmap *cm;
+ int console;
+#else
struct hwcmap *cm;
int console, i;
+#endif
console = (ta->ta_addr == xcfb_consaddr);
if (console) {
@@ -301,13 +312,20 @@
printf(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
sc->sc_dc->dc_depth);
+#if 1
+ cm = &sc->sc_cmap;
+ memset(cm, 255, sizeof(struct hwcmap)); /* XXX */
+ cm->r[0] = cm->g[0] = cm->b[0] = 0; /* XXX */
+#else
cm = &sc->sc_cmap;
cm->r[0] = cm->g[0] = cm->b[0] = 0;
for (i = 1; i < CMAP_SIZE; i++) {
cm->r[i] = cm->g[i] = cm->b[i] = 0xff;
}
+#endif
+ sc->sc_csr = IMS332_BPP_8 | IMS332_CSR_A_VTG_ENABLE;
- /* PMAG-DV emits no interrupt */
+ tc_intr_establish(parent, ta->ta_cookie, TC_IPL_TTY, xcfbintr, sc);
waa.console = console;
waa.scrdata = &xcfb_screenlist;
@@ -458,7 +476,19 @@
wsdisplay_cnattach(&xcfb_stdscreen, &dcp->dc_rcons,
0, 0, defattr);
xcfb_consaddr = addr;
- return(0);
+ return (0);
+}
+
+int
+xcfbintr(v)
+ void *v;
+{
+ int intr;
+
+ intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
+ intr &= ~XINE_INTR_VINT;
+ *(u_int32_t *)(ioasic_base + IOASIC_INTR) = intr;
+ return 1;
}
void
@@ -468,11 +498,32 @@
u_int32_t csr;
int i;
- csr = IMS332_BPP_8 | IMS332_CSR_A_DMA_DISABLE
- | IMS332_CSR_A_VTG_ENABLE | IMS332_CSR_A_DISABLE_CURSOR;
- ims332_write_reg(IMS332_REG_CSR_A, csr);
-
+ csr = *(u_int32_t *)(ioasic_base + IOASIC_CSR);
+ csr &= ~XINE_CSR_VDAC_ENABLE;
+ *(u_int32_t *)(ioasic_base + IOASIC_CSR) = csr;
+ DELAY(50);
+ csr |= XINE_CSR_VDAC_ENABLE;
+ *(u_int32_t *)(ioasic_base + IOASIC_CSR) = csr;
+ DELAY(50);
+ ims332_write_reg(IMS332_REG_BOOT, 0x2c);
+ ims332_write_reg(IMS332_REG_CSR_A,
+ IMS332_BPP_8|IMS332_CSR_A_DISABLE_CURSOR);
+ ims332_write_reg(IMS332_REG_HALF_SYNCH, 0x10);
+ ims332_write_reg(IMS332_REG_BACK_PORCH, 0x21);
+ ims332_write_reg(IMS332_REG_DISPLAY, 0x100);
+ ims332_write_reg(IMS332_REG_SHORT_DIS, 0x5d);
+ ims332_write_reg(IMS332_REG_BROAD_PULSE, 0x9f);
+ ims332_write_reg(IMS332_REG_LINE_TIME, 0x146);
+ ims332_write_reg(IMS332_REG_V_SYNC, 0x0c);
+ ims332_write_reg(IMS332_REG_V_PRE_EQUALIZE, 0x02);
+ ims332_write_reg(IMS332_REG_V_POST_EQUALIZE, 0x02);
+ ims332_write_reg(IMS332_REG_V_BLANK, 0x2a);
+ ims332_write_reg(IMS332_REG_V_DISPLAY, 0x600);
+ ims332_write_reg(IMS332_REG_LINE_START, 0x10);
+ ims332_write_reg(IMS332_REG_MEM_INIT, 0x0a);
ims332_write_reg(IMS332_REG_COLOR_MASK, 0xffffff);
+ ims332_write_reg(IMS332_REG_CSR_A,
+ IMS332_BPP_8|IMS332_CSR_A_VTG_ENABLE);
/* build sane colormap */
ims332_write_reg(IMS332_REG_LUT_BASE, 0);
@@ -497,25 +548,11 @@
xcfb_screenblank(sc)
struct xcfb_softc *sc;
{
- struct fb_devconfig *dc = sc->sc_dc;
- u_int16_t csr;
-
- if (dc->dc_blanked) {
- /* blank screen */
- ims332_write_reg(IMS332_REG_LUT_BASE, 0);
- ims332_write_reg(IMS332_REG_COLOR_MASK, 0);
- csr = ims332_read_reg(IMS332_REG_CSR_A);
- csr |= IMS332_CSR_A_DISABLE_CURSOR;
- ims332_write_reg(IMS332_REG_CSR_A, csr);
- }
- else {
- /* restore current colormap */
- ims332_loadcmap(&sc->sc_cmap);
- /* turnon hardware cursor */
- csr = ims332_read_reg(IMS332_REG_CSR_A);
- csr &= ~IMS332_CSR_A_DISABLE_CURSOR;
- ims332_write_reg(IMS332_REG_CSR_A, csr);
- }
+ if (sc->sc_dc->dc_blanked)
+ sc->sc_csr |= IMS332_CSR_A_FORCE_BLANK;
+ else
+ sc->sc_csr &= ~IMS332_CSR_A_FORCE_BLANK;
+ ims332_write_reg(IMS332_REG_CSR_A, sc->sc_csr);
}
static int
@@ -569,7 +606,6 @@
{
#define cc (&sc->sc_cursor)
int v, index, count;
- u_int32_t csr;
v = p->which;
if (v & WSDISPLAY_CURSOR_DOCMAP) {
@@ -603,12 +639,11 @@
}
if (v & WSDISPLAY_CURSOR_DOCUR) {
cc->cc_hot = p->hot;
- csr = ims332_read_reg(IMS332_REG_CSR_A);
if (p->enable)
- csr &= ~IMS332_CSR_A_DISABLE_CURSOR;
+ sc->sc_csr &= ~IMS332_CSR_A_DISABLE_CURSOR;
else
- csr |= IMS332_CSR_A_DISABLE_CURSOR;
- ims332_write_reg(IMS332_REG_CSR_A, csr);
+ sc->sc_csr |= IMS332_CSR_A_DISABLE_CURSOR;
+ ims332_write_reg(IMS332_REG_CSR_A, sc->sc_csr);
}
if (v & WSDISPLAY_CURSOR_DOPOS) {
set_curpos(sc, &p->pos);
@@ -666,9 +701,12 @@
{
struct wsdisplay_curpos *curpos = &sc->sc_cursor.cc_pos;
u_int32_t pos;
+ int s;
+ s = spltty();
pos = (curpos->x & 0xfff) << 12 | (curpos->y & 0xfff);
ims332_write_reg(IMS332_REG_CURSOR_LOC, pos);
+ splx(s);
}
void
@@ -726,12 +764,12 @@
ims332_read_reg(regno)
int regno;
{
- caddr_t imsreg = (caddr_t)IMS332_ADDRESS;
- caddr_t rptr = (caddr_t)IMS332_RPTR + (regno << 4);
+ caddr_t high8 = (caddr_t)(ioasic_base + IMS332_HIGH);
+ caddr_t low16 = (caddr_t)(ioasic_base + IMS332_RLOW) + (regno << 4);
u_int v0, v1;
- v1 = *(volatile u_int32_t *)imsreg;
- v0 = *(volatile u_int16_t *)rptr;
+ v1 = *(volatile u_int16_t *)high8;
+ v0 = *(volatile u_int16_t *)low16;
return (v1 & 0xff00) << 8 | v0;
}
@@ -740,9 +778,9 @@
int regno;
u_int32_t val;
{
- caddr_t imsreg = (caddr_t)IMS332_ADDRESS;
- caddr_t wptr = (caddr_t)IMS332_WPTR + (regno << 4);
+ caddr_t high8 = (caddr_t)(ioasic_base + IMS332_HIGH);
+ caddr_t low16 = (caddr_t)(ioasic_base + IMS332_WLOW) + (regno << 4);
- *(volatile u_int32_t *)imsreg = (val & 0xff0000) >> 8;
- *(volatile u_int16_t *)wptr = val;
+ *(volatile u_int16_t *)high8 = (val & 0xff0000) >> 8;
+ *(volatile u_int16_t *)low16 = val;
}
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