[src/trunk]: src/sys/arch/mips/include Add a comment to CACHE_LINE_SIZE / COH...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0168a89df75d
branches:  trunk
changeset: 936266:0168a89df75d
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Jul 23 15:24:37 2020 +0000

description:
Add a comment to CACHE_LINE_SIZE / COHERENCY_UNIT size defines

diffstat:

 sys/arch/mips/include/mips_param.h |  6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diffs (20 lines):

diff -r 98fe391f8202 -r 0168a89df75d sys/arch/mips/include/mips_param.h
--- a/sys/arch/mips/include/mips_param.h        Thu Jul 23 14:10:25 2020 +0000
+++ b/sys/arch/mips/include/mips_param.h        Thu Jul 23 15:24:37 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_param.h,v 1.42 2020/07/23 12:15:59 skrll Exp $    */
+/*     $NetBSD: mips_param.h,v 1.43 2020/07/23 15:24:37 skrll Exp $    */
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -80,6 +80,10 @@
 #define MSGBUFSIZE     NBPG            /* default message buffer size */
 #endif
 
+/*
+ * Most MIPS have a cache line size of 32 bytes, but Cavium chips
+ * have a line size 128bytes and we need to cover the larger size.
+ */
 #define COHERENCY_UNIT 128
 #define CACHE_LINE_SIZE        128