[src/trunk]: src/sys/arch/mips/cavium IPI_SHOOTDOWN needs to be IPL_SCHED. Sp...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/86a74e6ce651
branches:  trunk
changeset: 942741:86a74e6ce651
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Mon Aug 17 21:00:29 2020 +0000

description:
IPI_SHOOTDOWN needs to be IPL_SCHED. Spotted by nick.

diffstat:

 sys/arch/mips/cavium/octeon_intr.c |  40 ++++++++++++++++++++++++++++++-------
 1 files changed, 32 insertions(+), 8 deletions(-)

diffs (103 lines):

diff -r b6e0d9be901d -r 86a74e6ce651 sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Mon Aug 17 20:43:13 2020 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Mon Aug 17 21:00:29 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.22 2020/08/05 04:47:35 simonb Exp $  */
+/*     $NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $        */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.22 2020/08/05 04:47:35 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -173,12 +173,33 @@
                .ih_irq = CIU_INT_MBOX_15_0,
                .ih_ipl = IPL_HIGH,
        },
+       [1] = {
+               .ih_func = octeon_ipi_intr,
+               .ih_arg = (void *)(uintptr_t)__BITS(31,16),
+               .ih_irq = CIU_INT_MBOX_31_16,
+               .ih_ipl = IPL_SCHED,
+       },
 };
+
+static int ipi_prio[NIPIS] = {
+       [IPI_NOP] = IPL_HIGH,
+       [IPI_AST] = IPL_HIGH,
+       [IPI_SHOOTDOWN] = IPL_SCHED,
+       [IPI_SYNCICACHE] = IPL_HIGH,
+       [IPI_KPREEMPT] = IPL_HIGH,
+       [IPI_SUSPEND] = IPL_HIGH,
+       [IPI_HALT] = IPL_HIGH,
+       [IPI_XCALL] = IPL_HIGH,
+       [IPI_GENERIC] = IPL_HIGH,
+       [IPI_WDOG] = IPL_HIGH,
+};
+
 #endif
 
 static struct octeon_intrhand *octciu_intrs[NIRQS] = {
 #ifdef MULTIPROCESSOR
        [CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
+       [CIU_INT_MBOX_31_16] = &ipi_intrhands[1],
 #endif
 };
 
@@ -256,6 +277,7 @@
 #ifdef MULTIPROCESSOR
        // Enable the IPIs
        cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
+       cpu->cpu_ip3_enable[0] |= __BIT(CIU_INT_MBOX_31_16);
 #endif
 
        if (ci->ci_dev) {
@@ -514,10 +536,11 @@
 {
        struct cpu_info * const ci = curcpu();
        struct cpu_softc * const cpu = ci->ci_softc;
-       uint32_t ipi_mask = (uintptr_t) arg;
+       const uint32_t mbox_mask = (uintptr_t) arg;
+       uint32_t ipi_mask = mbox_mask;
 
-       KASSERTMSG(ci->ci_cpl == IPL_HIGH,
-           "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
+       KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+           "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
 
        ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
        if (ipi_mask == 0)
@@ -525,7 +548,7 @@
 
        mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
 
-       KASSERT(ipi_mask < __BIT(NIPIS));
+       KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));
 
 #if NWDOG > 0
        // Handle WDOG requests ourselves.
@@ -546,7 +569,7 @@
        atomic_or_64(&ci->ci_active_ipis, ipi_mask);
        atomic_and_64(&ci->ci_request_ipis, ~ipi_mask);
 
-       ipi_process(ci, ipi_mask);
+       ipi_process(ci, __SHIFTOUT(ipi_mask, mbox_mask));
 
        atomic_and_64(&ci->ci_active_ipis, ~ipi_mask);
 
@@ -571,7 +594,8 @@
                return -1;
 
        struct cpu_softc * const cpu = ci->ci_softc;
-       const uint32_t ipi_mask = __BIT(req);
+       const u_int ipi_shift = ipi_prio[req] == IPL_SCHED ? 16 : 0;
+       const uint32_t ipi_mask = __BIT(req + ipi_shift);
 
        atomic_or_64(&ci->ci_request_ipis, ipi_mask);