[src-draft/trunk]: src WIP: update dts for pinephone

To: source-changes-hg%NetBSD.org@localhost
Subject: [src-draft/trunk]: src WIP: update dts for pinephone
From: Taylor R Campbell <riastradh%NetBSD.org@localhost>
Date: Mon, 11 Jan 2021 21:07:19 +0000
details:   https://anonhg.NetBSD.org/src-all/rev/cc8aea39bf2e
branches:  trunk
changeset: 949385:cc8aea39bf2e
user:      Taylor R Campbell <riastradh%NetBSD.org@localhost>
date:      Tue Dec 01 06:55:48 2020 +0000

description:
WIP: update dts for pinephone

Upstream Pine64 Linux repository, branch pine64-kernel-5.9.y, commit:

https://gitlab.com/pine64-org/linux/-/commit/b0c492fcc502826cf73675ad89c00cb4dc475ad4

diffstat:

 distrib/sets/lists/dtb/ad.aarch64                                        |    3 +
 distrib/sets/lists/dtb/ad.aarch64eb                                      |    3 +
 sys/arch/arm/dts/sun50i-a64-cpu-opp.dtsi                                 |   81 +
 sys/arch/arm/dts/sun50i-a64-pinephone-1.0.dts                            |   49 +
 sys/arch/arm/dts/sun50i-a64-pinephone-1.1.dts                            |   68 +
 sys/arch/arm/dts/sun50i-a64-pinephone-1.2.dts                            |   80 +
 sys/arch/arm/dts/sun50i-a64-pinephone.dtsi                               |  746 ++++++++++
 sys/arch/arm/dts/sun50i-a64.dtsi                                         |    2 +
 sys/dtb/arm64/allwinner/Makefile                                         |    4 +
 sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |  378 +++-
 sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-a64-ccu.h    |    3 +-
 11 files changed, 1331 insertions(+), 86 deletions(-)

diffs (truncated from 1744 to 300 lines):

diff -r a4726a5f7e40 -r cc8aea39bf2e distrib/sets/lists/dtb/ad.aarch64
--- a/distrib/sets/lists/dtb/ad.aarch64 Mon Nov 30 22:26:30 2020 +0000
+++ b/distrib/sets/lists/dtb/ad.aarch64 Tue Dec 01 06:55:48 2020 +0000
@@ -15,6 +15,9 @@
 ./boot/dtb/allwinner/sun50i-a64-pine64-plus.dtb              dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-pine64.dtb                   dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-pinebook.dtb                 dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.0.dtb            dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.1.dtb            dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.2.dtb            dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-sopine-baseboard.dtb         dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-teres-i.dtb                  dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dtb     dtb-base-boot  dtb
diff -r a4726a5f7e40 -r cc8aea39bf2e distrib/sets/lists/dtb/ad.aarch64eb
--- a/distrib/sets/lists/dtb/ad.aarch64eb       Mon Nov 30 22:26:30 2020 +0000
+++ b/distrib/sets/lists/dtb/ad.aarch64eb       Tue Dec 01 06:55:48 2020 +0000
@@ -15,6 +15,9 @@
 ./boot/dtb/allwinner/sun50i-a64-pine64-plus.dtb              dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-pine64.dtb                   dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-pinebook.dtb                 dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.0.dtb            dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.1.dtb            dtb-base-boot  dtb
+./boot/dtb/allwinner/sun50i-a64-pinephone-1.2.dtb            dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-sopine-baseboard.dtb         dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-a64-teres-i.dtb                  dtb-base-boot  dtb
 ./boot/dtb/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dtb     dtb-base-boot  dtb
diff -r a4726a5f7e40 -r cc8aea39bf2e sys/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/dts/sun50i-a64-cpu-opp.dtsi  Tue Dec 01 06:55:48 2020 +0000
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Vasily khoruzhick <anarsoul%gmail.com@localhost>
+ */
+
+/ {
+       cpu0_opp_table: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+                opp-480000000 {
+                        opp-hz = /bits/ 64 <480000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+               opp-648000000 {
+                       opp-hz = /bits/ 64 <648000000>;
+                       opp-microvolt = <1040000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-816000000 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-912000000 {
+                       opp-hz = /bits/ 64 <912000000>;
+                       opp-microvolt = <1120000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-960000000 {
+                       opp-hz = /bits/ 64 <960000000>;
+                       opp-microvolt = <1160000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-1008000000 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1200000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-1056000000 {
+                       opp-hz = /bits/ 64 <1056000000>;
+                       opp-microvolt = <1240000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-1104000000 {
+                       opp-hz = /bits/ 64 <1104000000>;
+                       opp-microvolt = <1260000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp-1152000000 {
+                       opp-hz = /bits/ 64 <1152000000>;
+                       opp-microvolt = <1300000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+       };
+};
+
+&cpu0 {
+       operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu1 {
+       operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu2 {
+       operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu3 {
+       operating-points-v2 = <&cpu0_opp_table>;
+};
diff -r a4726a5f7e40 -r cc8aea39bf2e sys/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/dts/sun50i-a64-pinephone-1.0.dts     Tue Dec 01 06:55:48 2020 +0000
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous%megous.com@localhost>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+       model = "Pine64 PinePhone Developer Batch (1.0)";
+       compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
+};
+
+&anx7688 {
+       reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+       avdd33-supply = <&reg_dldo1>;
+};
+
+&axp803 {
+       x-powers,drive-vbus-en;
+};
+
+&codec_analog {
+       allwinner,internal-bias-resistor;
+};
+
+/*
+ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
+ * the VBUS status anyway. To avoid the pin from floating and to inform
+ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
+ */
+&reg_drivevbus {
+       vin-supply = <&reg_vcc5v0>;
+       status = "okay";
+};
+
+&reg_usb0_vbus {
+       gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+       enable-active-high;
+       vin-supply = <&reg_drivevbus>;
+};
+
+&ring_indicator {
+       gpios = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 */
+};
+
+&sgm3140 {
+       enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+       flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+};
diff -r a4726a5f7e40 -r cc8aea39bf2e sys/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/dts/sun50i-a64-pinephone-1.1.dts     Tue Dec 01 06:55:48 2020 +0000
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous%megous.com@localhost>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+       model = "Pine64 PinePhone Braveheart (1.1)";
+       compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
+};
+
+&anx7688 {
+       reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+       avdd33-supply = <&reg_dldo1>;
+};
+
+&axp803 {
+       x-powers,drive-vbus-en;
+};
+
+&backlight {
+       power-supply = <&reg_ldo_io0>;
+       /*
+        * PWM backlight circuit on this PinePhone revision was changed since
+        * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
+        * being off is around 20%. Duty cycle for the lowest brightness level
+        * also varries quite a bit between individual boards, so the lowest
+        * value here was chosen as a safe default.
+        */
+       brightness-levels = <
+               774  793  814  842
+               882  935  1003 1088
+               1192 1316 1462 1633
+               1830 2054 2309 2596
+               2916 3271 3664 4096>;
+       num-interpolated-steps = <50>;
+       default-brightness-level = <400>;
+};
+
+&codec_analog {
+       allwinner,internal-bias-resistor;
+};
+
+/*
+ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
+ * the VBUS status anyway. To avoid the pin from floating and to inform
+ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
+ */
+&reg_drivevbus {
+       vin-supply = <&reg_vcc5v0>;
+       status = "okay";
+};
+
+&reg_usb0_vbus {
+       gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+       enable-active-high;
+       vin-supply = <&reg_drivevbus>;
+};
+
+&ring_indicator {
+       gpios = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 */
+};
+
+&sgm3140 {
+       enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+       flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+};
diff -r a4726a5f7e40 -r cc8aea39bf2e sys/arch/arm/dts/sun50i-a64-pinephone-1.2.dts
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/dts/sun50i-a64-pinephone-1.2.dts     Tue Dec 01 06:55:48 2020 +0000
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous%megous.com@localhost>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+       model = "Pine64 PinePhone (1.2)";
+       compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64";
+
+       wifi_pwrseq: wifi_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+       };
+};
+
+&anx7688 {
+       reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+       avdd33-supply = <&reg_dcdc1>;
+};
+
+&axp803 {
+       x-powers,sense-vbus-en;
+};
+
+&backlight {
+       power-supply = <&reg_ldo_io0>;
+       /*
+        * PWM backlight circuit on this PinePhone revision was changed since 1.0,
+        * and the lowest PWM duty cycle that doesn't lead to backlight being off
+        * is around 10%. Duty cycle for the lowest brightness level also varries
+        * quite a bit between individual boards, so the lowest value here was
+        * chosen as a safe default.
+        */
+       brightness-levels = <
+               5000 5248 5506 5858 6345
+               6987 7805 8823 10062 11543
+               13287 15317 17654 20319 23336
+               26724 30505 34702 39335 44427
+               50000
+       >;
+       num-interpolated-steps = <50>;
+       default-brightness-level = <500>;
+};
+
+&lis3mdl {
+       /*
+        * Board revision 1.2 fixed routing of the interrupt to DRDY pin,
+        * enable interrupts.
+        */
+       interrupt-parent = <&pio>;
+       interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */
+};
+
+&mmc1 {
+       mmc-pwrseq = <&wifi_pwrseq>;
+};
+
+&reg_anx_vdd1v0 {
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