Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/aarch64/include Whitespace
details: https://anonhg.NetBSD.org/src/rev/db037d7e6656
branches: trunk
changeset: 992052:db037d7e6656
user: skrll <skrll%NetBSD.org@localhost>
date: Sun Aug 12 17:16:18 2018 +0000
description:
Whitespace
diffstat:
sys/arch/aarch64/include/armreg.h | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diffs (25 lines):
diff -r 6de71ea2fd56 -r db037d7e6656 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Sun Aug 12 17:15:56 2018 +0000
+++ b/sys/arch/aarch64/include/armreg.h Sun Aug 12 17:16:18 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.16 2018/08/09 10:27:17 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.17 2018/08/12 17:16:18 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -929,7 +929,6 @@
#define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
-
// ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
#define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF
#define ID_AA64PFR0_EL1_GIC_SHIFT 24
@@ -1088,7 +1087,6 @@
gtmr_cntp_ctl_write(uint32_t val)
{
-
reg_cntp_ctl_el0_write(val);
}
Home |
Main Index |
Thread Index |
Old Index