[src/trunk]: src/sys/dev/pci Use PCI-SIG official acronyms:

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/07aa89d65574
branches:  trunk
changeset: 1024129:07aa89d65574
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Sun Oct 10 23:28:36 2021 +0000

description:
Use PCI-SIG official acronyms:

 - RP stands for Root Port.
 - RC stands for Root Complex.
 - RCIEP stands for Root Complex Integrated End Point.

diffstat:

 sys/dev/pci/pci.c      |   6 +++---
 sys/dev/pci/pci_subr.c |  18 +++++++++---------
 sys/dev/pci/pcireg.h   |  16 ++++++++--------
 sys/dev/pci/ppb.c      |   8 ++++----
 4 files changed, 24 insertions(+), 24 deletions(-)

diffs (175 lines):

diff -r 4baf599aec30 -r 07aa89d65574 sys/dev/pci/pci.c
--- a/sys/dev/pci/pci.c Sun Oct 10 23:02:10 2021 +0000
+++ b/sys/dev/pci/pci.c Sun Oct 10 23:28:36 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci.c,v 1.162 2021/09/15 17:33:08 thorpej Exp $        */
+/*     $NetBSD: pci.c,v 1.163 2021/10/10 23:28:36 msaitoh Exp $        */
 
 /*
  * Copyright (c) 1995, 1996, 1997, 1998
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.162 2021/09/15 17:33:08 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.163 2021/10/10 23:28:36 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -735,7 +735,7 @@
                if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS,
                    &pciecap, &capreg) != 0) {
                        switch (PCIE_XCAP_TYPE(capreg)) {
-                       case PCIE_XCAP_TYPE_ROOT:
+                       case PCIE_XCAP_TYPE_RP:
                        case PCIE_XCAP_TYPE_DOWN:
                        case PCIE_XCAP_TYPE_PCI2PCIE:
                                downstream_port = true;
diff -r 4baf599aec30 -r 07aa89d65574 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Sun Oct 10 23:02:10 2021 +0000
+++ b/sys/dev/pci/pci_subr.c    Sun Oct 10 23:28:36 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $   */
+/*     $NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -914,7 +914,7 @@
 
                if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                        reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
-                       if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
+                       if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)
                                subclass = PCI_SUBCLASS_SYSTEM_RCEC;
                }
        }
@@ -1861,7 +1861,7 @@
                printf("Legacy PCI Express Endpoint device\n");
                check_upstreamport = true;
                break;
-       case PCIE_XCAP_TYPE_ROOT:       /* 0x4 */
+       case PCIE_XCAP_TYPE_RP:         /* 0x4 */
                printf("Root Port of PCI Express Root Complex\n");
                check_slot = true;
                break;
@@ -1882,10 +1882,10 @@
                /* Upstream port is not PCIe */
                check_slot = true;
                break;
-       case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
+       case PCIE_XCAP_TYPE_RCIEP:      /* 0x9 */
                printf("Root Complex Integrated Endpoint\n");
                break;
-       case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
+       case PCIE_XCAP_TYPE_RC_EVNTC:   /* 0xa */
                printf("Root Complex Event Collector\n");
                break;
        default:
@@ -2930,8 +2930,8 @@
            extcapoff + PCI_AER_ROOTERR_CMD);
 
        switch (pcie_devtype) {
-       case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
-       case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
+       case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */
+       case PCIE_XCAP_TYPE_RC_EVNTC:   /* Root Complex Event Collector */
                reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
                printf("    Root Error Command register: 0x%08x\n", reg);
                pci_conf_print_aer_cap_rooterr_cmd(reg);
@@ -4149,7 +4149,7 @@
        if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                uint32_t t = regs[o2i(pcie_capoff)];
 
-               if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
+               if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN))
                        onoff("Link Activation Supported", reg,
                            PCI_L1PM_CAP_LA);
        }
diff -r 4baf599aec30 -r 07aa89d65574 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Sun Oct 10 23:02:10 2021 +0000
+++ b/sys/dev/pci/pcireg.h      Sun Oct 10 23:28:36 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.160 2021/10/10 07:20:01 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.161 2021/10/10 23:28:36 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -983,13 +983,13 @@
 #define        PCIE_XCAP_TYPE(x)       __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)
 #define         PCIE_XCAP_TYPE_PCIE_DEV        0x0
 #define         PCIE_XCAP_TYPE_PCI_DEV         0x1
-#define         PCIE_XCAP_TYPE_ROOT            0x4
+#define         PCIE_XCAP_TYPE_RP              0x4
 #define         PCIE_XCAP_TYPE_UP              0x5
 #define         PCIE_XCAP_TYPE_DOWN            0x6
 #define         PCIE_XCAP_TYPE_PCIE2PCI        0x7
 #define         PCIE_XCAP_TYPE_PCI2PCIE        0x8
-#define         PCIE_XCAP_TYPE_ROOT_INTEP      0x9
-#define         PCIE_XCAP_TYPE_ROOT_EVNTC      0xa
+#define         PCIE_XCAP_TYPE_RCIEP           0x9
+#define         PCIE_XCAP_TYPE_RC_EVNTC        0xa
 #define PCIE_XCAP_SI           __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
 #define PCIE_XCAP_IRQ          __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)
 #define PCIE_DCAP      0x04    /* Device Capabilities Register */
@@ -1198,12 +1198,12 @@
  * Other than Root Complex Integrated Endpoint and Root Complex Event Collector
  * have link related registers.
  */
-#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \
-           ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_RCIEP) &&   \
+           ((type) != PCIE_XCAP_TYPE_RC_EVNTC))
 
 /* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
-#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \
-           ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_RP) || \
+           ((type) == PCIE_XCAP_TYPE_RC_EVNTC))
 
 
 /*
diff -r 4baf599aec30 -r 07aa89d65574 sys/dev/pci/ppb.c
--- a/sys/dev/pci/ppb.c Sun Oct 10 23:02:10 2021 +0000
+++ b/sys/dev/pci/ppb.c Sun Oct 10 23:28:36 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ppb.c,v 1.73 2021/08/07 16:19:14 thorpej Exp $ */
+/*     $NetBSD: ppb.c,v 1.74 2021/10/10 23:28:36 msaitoh Exp $ */
 
 /*
  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.73 2021/08/07 16:19:14 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.74 2021/10/10 23:28:36 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_ppb.h"
@@ -146,7 +146,7 @@
        case PCIE_XCAP_TYPE_PCI_DEV:
                aprint_normal("Legacy PCI-E Endpoint device");
                break;
-       case PCIE_XCAP_TYPE_ROOT:
+       case PCIE_XCAP_TYPE_RP:
                aprint_normal("Root Port of PCI-E Root Complex");
                break;
        case PCIE_XCAP_TYPE_UP:
@@ -167,7 +167,7 @@
        }
 
        switch (devtype) {
-       case PCIE_XCAP_TYPE_ROOT:
+       case PCIE_XCAP_TYPE_RP:
        case PCIE_XCAP_TYPE_DOWN:
        case PCIE_XCAP_TYPE_PCI2PCIE:
                reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);