[src/trunk]: src/sys/dev/pci Use unsigned to avoid undefined behavior. Found ...

To: source-changes-hg%NetBSD.org@localhost
Subject: [src/trunk]: src/sys/dev/pci Use unsigned to avoid undefined behavior. Found ...
From: msaitoh <msaitoh%NetBSD.org@localhost>
Date: Fri, 17 Jun 2022 07:54:41 +0000
details:   https://anonhg.NetBSD.org/src/rev/3e302c156e10
branches:  trunk
changeset: 366811:3e302c156e10
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Jun 17 05:49:35 2022 +0000

description:
Use unsigned to avoid undefined behavior. Found by kUBSan.

diffstat:

 sys/dev/pci/if_ixlreg.h |  74 ++++++++++++++++++++++++------------------------
 1 files changed, 37 insertions(+), 37 deletions(-)

diffs (273 lines):

diff -r df0d08a36b92 -r 3e302c156e10 sys/dev/pci/if_ixlreg.h
--- a/sys/dev/pci/if_ixlreg.h   Fri Jun 17 01:47:45 2022 +0000
+++ b/sys/dev/pci/if_ixlreg.h   Fri Jun 17 05:49:35 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_ixlreg.h,v 1.1 2019/12/10 12:08:52 yamaguchi Exp $  */
+/*     $NetBSD: if_ixlreg.h,v 1.2 2022/06/17 05:49:35 msaitoh Exp $    */
 
 /******************************************************************************
 
@@ -277,7 +277,7 @@
 #define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT    0
 #define I40E_PRTDCB_FCTTVN_TTV_2N_MASK     I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
 #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
-#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
+#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK  I40E_MASK(0xFFFFU, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
 #define I40E_PRTDCB_GENC                    0x00083000 /* Reset: CORER */
 #define I40E_PRTDCB_GENC_RESERVED_1_SHIFT   0
 #define I40E_PRTDCB_GENC_RESERVED_1_MASK    I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
@@ -288,7 +288,7 @@
 #define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
 #define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK  I40E_MASK(0x1U, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT       16
-#define I40E_PRTDCB_GENC_PFCLDA_MASK        I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
+#define I40E_PRTDCB_GENC_PFCLDA_MASK        I40E_MASK(0xFFFFU, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
 #define I40E_PRTDCB_GENS                   0x00083020 /* Reset: CORER */
 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK  I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
@@ -569,7 +569,7 @@
 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
 #define I40E_GLGEN_MSRWD_MDIWRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
-#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
+#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK  I40E_MASK(0xFFFFU, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
 #define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
@@ -1372,7 +1372,7 @@
 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
 #define I40E_PRTGL_SAH_FC_SAH_MASK  I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
 #define I40E_PRTGL_SAH_MFS_SHIFT    16
-#define I40E_PRTGL_SAH_MFS_MASK     I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
+#define I40E_PRTGL_SAH_MFS_MASK     I40E_MASK(0xFFFFU, I40E_PRTGL_SAH_MFS_SHIFT)
 #define I40E_PRTGL_SAL              0x001E2120 /* Reset: GLOBR */
 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
 #define I40E_PRTGL_SAL_FC_SAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
@@ -1570,7 +1570,7 @@
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT   0
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK    I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
-#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
+#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK  I40E_MASK(0xFFFFU, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
 #define I40E_PRT_MNG_METF(_i)            (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_METF_MAX_INDEX      3
 #define I40E_PRT_MNG_METF_ETYPE_SHIFT    0
@@ -1723,7 +1723,7 @@
 #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
 #define I40E_GLNVM_SRDATA_WRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
-#define I40E_GLNVM_SRDATA_RDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
+#define I40E_GLNVM_SRDATA_RDDATA_MASK  I40E_MASK(0xFFFFU, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
 #define I40E_GLNVM_ULD                          0x000B6008 /* Reset: POR */
 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT     0
 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK      I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
@@ -1847,7 +1847,7 @@
 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
 #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT     16
-#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK      I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
+#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK      I40E_MASK(0xFFFFU, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
 #define I40E_GLPCI_GSCN_0_3(_i)                 (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
 #define I40E_GLPCI_GSCN_0_3_MAX_INDEX           3
 #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
@@ -1988,7 +1988,7 @@
 #define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
 #define I40E_PFPCI_DEVID_PF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
 #define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
-#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
+#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK  I40E_MASK(0xFFFFU, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
 #define I40E_PFPCI_FACTPS                        0x0009C180 /* Reset: FLR */
 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK  I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
@@ -2023,7 +2023,7 @@
 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
 #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
-#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
+#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK  I40E_MASK(0xFFFFU, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
 #define I40E_PFPCI_VF_FLUSH_DONE                  0x0000E400 /* Reset: PCIR */
 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1U, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
@@ -3088,7 +3088,7 @@
 #define I40E_GLPM_WUMC_RESERVED_4_SHIFT   3
 #define I40E_GLPM_WUMC_RESERVED_4_MASK    I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
 #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT    16
-#define I40E_GLPM_WUMC_MNG_WU_PF_MASK     I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
+#define I40E_GLPM_WUMC_MNG_WU_PF_MASK     I40E_MASK(0xFFFFU, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
 #define I40E_PFPM_APM            0x000B8080 /* Reset: POR */
 #define I40E_PFPM_APM_APME_SHIFT 0
 #define I40E_PFPM_APM_APME_MASK  I40E_MASK(0x1U, I40E_PFPM_APM_APME_SHIFT)
@@ -4060,7 +4060,7 @@
 #define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
+#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
 #define I40E_GLPCI_CUR_CLNT_PIPEMON                  0x0009CA20 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT)
@@ -4068,77 +4068,77 @@
 #define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_MNG_RSVD                  0x0009c594 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_PMAT_ALWD                  0x0009c510 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_PMAT_RSVD                  0x0009c590 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_RLAN_ALWD                  0x0009c500 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_RLAN_RSVD                  0x0009c580 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_RXPE_ALWD                  0x0009c508 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_RXPE_RSVD                  0x0009c588 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TDPU_ALWD                  0x0009c518 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TDPU_RSVD                  0x0009c598 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TLAN_ALWD                  0x0009c504 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TLAN_RSVD                  0x0009c584 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TXPE_ALWD                  0x0009c50C /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_TXPE_RSVD                  0x0009c58c /* Reset: PCIR */
 #define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
+#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
 #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON                  0x0009CA28 /* Reset: PCIR */
 #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT)
 #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT        16
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)
+#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)
 
 #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT    4
 #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK     I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
@@ -4162,37 +4162,37 @@
 #define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_PMAT_ALWD                  0x0009CB10 /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_RLAN_ALWD                  0x0009CB00 /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_RXPE_ALWD                  0x0009CB08 /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_TLAN_ALWD                  0x0009CB04 /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_TPDU_ALWD                  0x0009CB18 /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
 #define I40E_GLPCI_WATMK_TXPE_ALWD                  0x0009CB0c /* Reset: PCIR */
 #define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0
 #define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT)
 #define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT        16
-#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
+#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK         I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
 #define I40E_GLPE_CPUSTATUS0                    0x0000D040 /* Reset: PE_CORER */
 #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
 #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
@@ -4329,7 +4329,7 @@
 #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
 #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
 #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
-#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
+#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFFU, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
 #define I40E_PFPE_CQPTAIL                  0x00008080 /* Reset: PFR */
 #define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT     0
 #define I40E_PFPE_CQPTAIL_WQTAIL_MASK      I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
@@ -4493,7 +4493,7 @@
 #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
 #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
 #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
-#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
+#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFFU, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
 #define I40E_VFPE_CQPTAIL(_VF)             (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFPE_CQPTAIL_MAX_INDEX        127
 #define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT     0
@@ -5315,7 +5315,7 @@
 #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
 #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
 #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
+#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK  I40E_MASK(0xFFFFU, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
 #define I40E_VFPE_CQPTAIL1                  0x0000A000 /* Reset: VFR */
 #define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT     0
 #define I40E_VFPE_CQPTAIL1_WQTAIL_MASK      I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
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