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[xsrc/trunk]: xsrc/external/mit/libdrm/dist merge libdrm 2.4.114.
details: https://anonhg.NetBSD.org/xsrc/rev/690ec8d96207
branches: trunk
changeset: 7248:690ec8d96207
user: mrg <mrg%NetBSD.org@localhost>
date: Sat Nov 12 02:07:07 2022 +0000
description:
merge libdrm 2.4.114.
diffstat:
external/mit/libdrm/dist/.gitlab-ci/debian-install.sh | 66 -
external/mit/libdrm/dist/amdgpu/amdgpu_bo.c | 2 +-
external/mit/libdrm/dist/include/drm/i915_drm.h | 2083 +++++++++++++++-
external/mit/libdrm/dist/intel/intel_bufmgr_gem.c | 56 +-
external/mit/libdrm/dist/tests/modetest/modetest.c | 8 +-
external/mit/libdrm/dist/xf86atomic.h | 2 +-
external/mit/libdrm/dist/xf86drm.c | 50 +-
external/mit/libdrm/dist/xf86drm.h | 3 +
external/mit/libdrm/dist/xf86drmMode.c | 49 +
external/mit/libdrm/dist/xf86drmMode.h | 32 +
10 files changed, 2109 insertions(+), 242 deletions(-)
diffs (truncated from 2920 to 300 lines):
diff -r 8e7445b5b36a -r 690ec8d96207 external/mit/libdrm/dist/.gitlab-ci/debian-install.sh
--- a/external/mit/libdrm/dist/.gitlab-ci/debian-install.sh Sat Nov 12 02:04:41 2022 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-#!/usr/bin/env bash
-set -o errexit
-set -o xtrace
-
-export DEBIAN_FRONTEND=noninteractive
-
-CROSS_ARCHITECTURES=(i386 armhf arm64 ppc64el)
-for arch in ${CROSS_ARCHITECTURES[@]}; do
- dpkg --add-architecture $arch
-done
-
-apt-get install -y \
- ca-certificates
-
-sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
-echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
-
-apt-get update
-
-# Use newer packages from backports by default
-cat >/etc/apt/preferences <<EOF
-Package: *
-Pin: release a=buster-backports
-Pin-Priority: 500
-EOF
-
-apt-get dist-upgrade -y
-
-apt-get install -y --no-remove \
- build-essential \
- docbook-xsl \
- libatomic-ops-dev \
- libcairo2-dev \
- libcunit1-dev \
- libpciaccess-dev \
- meson \
- ninja-build \
- pkg-config \
- python3 \
- python3-pip \
- python3-wheel \
- python3-setuptools \
- python3-docutils \
- valgrind
-
-for arch in ${CROSS_ARCHITECTURES[@]}; do
- cross_file=/cross_file-$arch.txt
-
- # Cross-build libdrm deps
- apt-get install -y --no-remove \
- libcairo2-dev:$arch \
- libpciaccess-dev:$arch \
- crossbuild-essential-$arch
-
- # Generate cross build files for Meson
- /usr/share/meson/debcrossgen --arch $arch -o $cross_file
-
- # Work around a bug in debcrossgen that should be fixed in the next release
- if [ $arch = i386 ]; then
- sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" $cross_file
- fi
-done
-
-
-# Test that the oldest Meson version we claim to support is still supported
-pip3 install meson==0.46
diff -r 8e7445b5b36a -r 690ec8d96207 external/mit/libdrm/dist/amdgpu/amdgpu_bo.c
--- a/external/mit/libdrm/dist/amdgpu/amdgpu_bo.c Sat Nov 12 02:04:41 2022 +0000
+++ b/external/mit/libdrm/dist/amdgpu/amdgpu_bo.c Sat Nov 12 02:07:07 2022 +0000
@@ -533,7 +533,7 @@
amdgpu_bo_handle *buf_handle,
uint64_t *offset_in_bo)
{
- struct amdgpu_bo *bo;
+ struct amdgpu_bo *bo = NULL;
uint32_t i;
int r = 0;
diff -r 8e7445b5b36a -r 690ec8d96207 external/mit/libdrm/dist/include/drm/i915_drm.h
--- a/external/mit/libdrm/dist/include/drm/i915_drm.h Sat Nov 12 02:04:41 2022 +0000
+++ b/external/mit/libdrm/dist/include/drm/i915_drm.h Sat Nov 12 02:07:07 2022 +0000
@@ -55,15 +55,15 @@
* cause the related events to not be seen.
*
* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
- * the GPU. The value supplied with the event is always 1. NOTE: Disable
+ * GPU. The value supplied with the event is always 1. NOTE: Disable
* reset via module parameter will cause this event to not be seen.
*/
#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
-/*
- * i915_user_extension: Base class for defining a chain of extensions
+/**
+ * struct i915_user_extension - Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
@@ -76,12 +76,58 @@
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
* the boundary with pointers encapsulated inside u64.
+ *
+ * Example chaining:
+ *
+ * .. code-block:: C
+ *
+ * struct i915_user_extension ext3 {
+ * .next_extension = 0, // end
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext2 {
+ * .next_extension = (uintptr_t)&ext3,
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext1 {
+ * .next_extension = (uintptr_t)&ext2,
+ * .name = ...,
+ * };
+ *
+ * Typically the struct i915_user_extension would be embedded in some uAPI
+ * struct, and in this case we would feed it the head of the chain(i.e ext1),
+ * which would then apply all of the above extensions.
+ *
*/
struct i915_user_extension {
+ /**
+ * @next_extension:
+ *
+ * Pointer to the next struct i915_user_extension, or zero if the end.
+ */
__u64 next_extension;
+ /**
+ * @name: Name of the extension.
+ *
+ * Note that the name here is just some integer.
+ *
+ * Also note that the name space for this is not global for the whole
+ * driver, but rather its scope/meaning is limited to the specific piece
+ * of uAPI which has embedded the struct i915_user_extension.
+ */
__u32 name;
- __u32 flags; /* All undefined bits must be zero. */
- __u32 rsvd[4]; /* Reserved for future use; must be zero. */
+ /**
+ * @flags: MBZ
+ *
+ * All undefined bits must be zero.
+ */
+ __u32 flags;
+ /**
+ * @rsvd: MBZ
+ *
+ * Reserved for future use; must be zero.
+ */
+ __u32 rsvd[4];
};
/*
@@ -108,25 +154,102 @@
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
-
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
+ * There may be more than one engine fulfilling any role within the system.
+ * Each engine of a class is given a unique instance number and therefore
+ * any engine can be specified by its class:instance tuplet. APIs that allow
+ * access to any engine in the system will use struct i915_engine_class_instance
+ * for this identification.
+ */
+struct i915_engine_class_instance {
+ /**
+ * @engine_class:
+ *
+ * Engine class from enum drm_i915_gem_engine_class
+ */
+ __u16 engine_class;
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+ /**
+ * @engine_instance:
+ *
+ * Engine instance.
+ */
+ __u16 engine_instance;
+};
+
+/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
*/
@@ -163,8 +286,9 @@
#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
-
-#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
+
+#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
@@ -343,6 +467,9 @@
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
+#define DRM_I915_GEM_VM_CREATE 0x3a
+#define DRM_I915_GEM_VM_DESTROY 0x3b
+#define DRM_I915_GEM_CREATE_EXT 0x3c
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -375,10 +502,12 @@
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
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