[src/trunk]: src/sys/dev/pci Add quirk setting for some Intel eMMC devices.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f1e83c21fe73
branches:  trunk
changeset: 372923:f1e83c21fe73
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu Jan 05 14:50:14 2023 +0000

description:
Add quirk setting for some Intel eMMC devices.

 On some Intel eMMC controllers, the driver reports "autoconfiguration error:
couldn't enable card: 60" even though they really have eMMC device.
This change fixes the problem on some machines. It might be required more
quirks for newer devices (or HS400 support). At least, this change fixes the
problem on GIGABYTE MA10-ST0.

diffstat:

 sys/dev/pci/sdhc_pci.c |  98 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 95 insertions(+), 3 deletions(-)

diffs (126 lines):

diff -r a1430a2734bc -r f1e83c21fe73 sys/dev/pci/sdhc_pci.c
--- a/sys/dev/pci/sdhc_pci.c    Thu Jan 05 09:57:39 2023 +0000
+++ b/sys/dev/pci/sdhc_pci.c    Thu Jan 05 14:50:14 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: sdhc_pci.c,v 1.20 2023/01/04 03:24:00 msaitoh Exp $    */
+/*     $NetBSD: sdhc_pci.c,v 1.21 2023/01/05 14:50:14 msaitoh Exp $    */
 /*     $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $        */
 
 /*
@@ -18,7 +18,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.20 2023/01/04 03:24:00 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.21 2023/01/05 14:50:14 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
@@ -161,7 +161,8 @@
                0xffff,
                0xffff,
                ~0,
-               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
        },
 
        {
@@ -172,6 +173,97 @@
                ~0,
                SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
        },
+
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_C3K_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC2,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_APL_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_GLK_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_3HS_U_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_495_YU_PCIE_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_CMTLK_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_JSL_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
+       {
+               PCI_VENDOR_INTEL,
+               PCI_PRODUCT_INTEL_EHL_EMMC,
+               0xffff,
+               0xffff,
+               ~0,
+               SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
+               SDHC_PCI_QUIRK_NO_PWR0
+       },
 };
 
 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *);