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[src/trunk]: src/sys/dev/pci Added support for the Aquantia (Marvell) AQC113 ...
details: https://anonhg.NetBSD.org/src/rev/ab619f1a60a1
branches: trunk
changeset: 373043:ab619f1a60a1
user: ryo <ryo%NetBSD.org@localhost>
date: Sat Jan 14 13:20:15 2023 +0000
description:
Added support for the Aquantia (Marvell) AQC113 10G Network Adapter and the variants, to aq(4)
diffstat:
sys/dev/pci/if_aq.c | 1519 ++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 1311 insertions(+), 208 deletions(-)
diffs (truncated from 2276 to 300 lines):
diff -r 19e8d67b610c -r ab619f1a60a1 sys/dev/pci/if_aq.c
--- a/sys/dev/pci/if_aq.c Sat Jan 14 13:19:31 2023 +0000
+++ b/sys/dev/pci/if_aq.c Sat Jan 14 13:20:15 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_aq.c,v 1.42 2023/01/14 13:17:50 ryo Exp $ */
+/* $NetBSD: if_aq.c,v 1.43 2023/01/14 13:20:15 ryo Exp $ */
/**
* aQuantia Corporation Network Driver
@@ -62,7 +62,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.42 2023/01/14 13:17:50 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.43 2023/01/14 13:20:15 ryo Exp $");
#ifdef _KERNEL_OPT
#include "opt_if_aq.h"
@@ -116,19 +116,29 @@
#define AQ_RSS_HASHKEY_SIZE 40
#define AQ_RSS_INDIRECTION_TABLE_MAX 64
-#define AQ_JUMBO_MTU_REV_A 9000
-#define AQ_JUMBO_MTU_REV_B 16338
+#define AQ1_JUMBO_MTU_REV_A 9000
+#define AQ1_JUMBO_MTU_REV_B 16338
+#define AQ2_JUMBO_MTU 16338
/*
* TERMINOLOGY
+ * ATL (AQ1) = Atlantic. AQC100,107-109,111,112.
+ * ATL2 (AQ2) = Atlantic2. AQC113-116.
* MPI = MAC PHY INTERFACE?
* RPO = RX Protocol Offloading
* TPO = TX Protocol Offloading
* RPF = RX Packet Filter
* TPB = TX Packet buffer
* RPB = RX Packet buffer
+ * ART = Action Resolver Table
+ * TC = Traffic Class
*/
+enum aq_hwtype {
+ HWTYPE_AQ1,
+ HWTYPE_AQ2
+};
+
/* registers */
#define AQ_FW_SOFTRESET_REG 0x0000
#define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */
@@ -136,6 +146,7 @@
#define AQ_FW_VERSION_REG 0x0018
#define AQ_HW_REVISION_REG 0x001c
+#define AQ2_HW_FPGA_VERSION_REG 0x00f4 /* AQ2 */
#define AQ_GLB_NVR_INTERFACE1_REG 0x0100
#define AQ_FW_MBOX_CMD_REG 0x0200
@@ -182,7 +193,8 @@
#define RBL_STATUS_HOST_BOOT 0x0000f1a7
#define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4)
-#define AQ_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2)
+#define AQ1_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2)
+#define AQ2_ART_SEM_REG AQ_FW_GLB_CPU_SEM_REG(3)
#define AQ_FW_GLB_CTL2_REG 0x0404
#define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1)
@@ -194,7 +206,7 @@
#define AQ_PCI_REG_CONTROL_6_REG 0x1014
-// msix bitmap */
+/* msix bitmap */
#define AQ_INTR_STATUS_REG 0x2000 /* intr status */
#define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */
#define AQ_INTR_MASK_REG 0x2060 /* intr mask set */
@@ -212,7 +224,7 @@
/* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */
#define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4)
-#define AQ_B0_ERR_INT 8U
+#define AQ_B0_ERR_INT 8
#define AQ_INTR_CTRL_REG 0x2300
#define AQ_INTR_CTRL_IRQMODE __BITS(1,0)
@@ -231,8 +243,9 @@
#define FW_MPI_RESETCTRL_RESET_DIS __BIT(29)
#define RX_SYSCONTROL_REG 0x5000
-#define RX_SYSCONTROL_RPB_DMA_LOOPBACK __BIT(6)
-#define RX_SYSCONTROL_RPF_TPO_LOOPBACK __BIT(8)
+#define RX_SYSCONTROL_RPF_TPO_SYS_LOOPBACK __BIT(8)
+#define RX_SYSCONTROL_RPB_DMA_SYS_LOOPBACK __BIT(6)
+#define RX_SYSCONTROL_RPB_DMA_NET_LOOPBACK __BIT(4)
#define RX_SYSCONTROL_RESET_DIS __BIT(29)
#define RX_TCP_RSS_HASH_REG 0x5040
@@ -252,14 +265,19 @@
#define RPF_L2BC_ACTION __BITS(12,14)
#define RPF_L2BC_THRESHOLD __BITS(31,16)
-/* RPF_L2UC_*_REG[34] (actual [38]?) */
+/* RPF_L2UC_*_REG[34] (AQ2 has [38]) */
#define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8)
#define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8)
#define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0)
#define RPF_L2UC_MSW_ACTION __BITS(18,16)
+#define RPF_L2UC_MSW_TAG __BITS(27,22) /* AQ2 */
#define RPF_L2UC_MSW_EN __BIT(31)
-#define AQ_HW_MAC_OWN 0 /* index of own address */
-#define AQ_HW_MAC_NUM 34
+
+#define AQ_HW_MAC_OWN 0 /* index of own address */
+#define AQ1_HW_MAC_NUM 34
+#define AQ2_HW_MAC_NUM 38
+#define AQ_HW_MAC_NUM(sc) \
+ (HWTYPE_AQ2_P((sc)) ? AQ2_HW_MAC_NUM : AQ1_HW_MAC_NUM)
/* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
#define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4)
@@ -283,6 +301,7 @@
#define RPF_VLAN_FILTER_RXQ_EN __BIT(28)
#define RPF_VLAN_FILTER_RXQ __BITS(24,20)
#define RPF_VLAN_FILTER_ACTION __BITS(18,16)
+#define RPF_VLAN_FILTER_TAG __BITS(15,12) /* AQ2 */
#define RPF_VLAN_FILTER_ID __BITS(11,0)
/* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
@@ -423,8 +442,9 @@
#define RX_DMA_COALESCED_PKT_CNT_REG 0x6820
#define TX_SYSCONTROL_REG 0x7000
-#define TX_SYSCONTROL_TPB_DMA_LOOPBACK __BIT(6)
-#define TX_SYSCONTROL_TPO_PKT_LOOPBACK __BIT(7)
+#define TX_SYSCONTROL_TPO_PKT_SYS_LOOPBACK __BIT(7)
+#define TX_SYSCONTROL_TPB_DMA_SYS_LOOPBACK __BIT(6)
+#define TX_SYSCONTROL_TPB_DMA_NET_LOOPBACK __BIT(4)
#define TX_SYSCONTROL_RESET_DIS __BIT(29)
#define TX_TPO2_REG 0x7040
@@ -449,8 +469,10 @@
#define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27)
#define TPS_DESC_TCT_WEIGHT __BITS(8,0)
-#define AQ_HW_TXBUF_MAX 160
-#define AQ_HW_RXBUF_MAX 320
+#define AQ1_HW_TXBUF_MAX 160
+#define AQ1_HW_RXBUF_MAX 320
+#define AQ2_HW_TXBUF_MAX 128
+#define AQ2_HW_RXBUF_MAX 192
#define TPO_HWCSUM_REG 0x7800
#define TPO_HWCSUM_IP4CSUM_EN __BIT(1)
@@ -467,7 +489,9 @@
#define TPB_TX_BUF_REG 0x7900
#define TPB_TX_BUF_EN __BIT(0)
#define TPB_TX_BUF_SCP_INS_EN __BIT(2)
-#define TPB_TX_BUF_TC_MODE_EN __BIT(8)
+#define TPB_TX_BUF_CLK_GATE_EN __BIT(5)
+#define TPB_TX_BUF_TC_MODE __BIT(8)
+#define TPB_TX_BUF_TC_Q_RAND_MAP_EN __BIT(9) /* AQ2 */
/* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */
#define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10)
@@ -508,6 +532,345 @@
#define TX_INTR_MODERATION_CTL_MIN __BITS(15,8)
#define TX_INTR_MODERATION_CTL_MAX __BITS(24,16)
+/* AQ2 (ATL2) registers */
+#define AQ2_QUEUE_MODE 0x0c9c
+
+#define AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG 0x0e00
+#define AQ2_MIF_HOST_FINISHED_STATUS_READ_REG 0x0e04
+#define AQ2_MIF_HOST_FINISHED_STATUS_ACK __BIT(0)
+
+#define AQ2_MCP_HOST_REQ_INT_REG 0x0f00
+#define AQ2_MCP_HOST_REQ_INT_READY __BIT(0)
+#define AQ2_MCP_HOST_REQ_INT_SET_REG 0x0f04
+#define AQ2_MCP_HOST_REQ_INT_CLR_REG 0x0f08
+
+#define AQ2_PHI_EXT_TAG_REG 0x1000
+#define AQ2_PHI_EXT_TAG_ENABLE __BIT(5)
+
+#define AQ2_MIF_BOOT_REG 0x3040
+#define AQ2_MIF_BOOT_HOST_DATA_LOADED __BIT(16)
+#define AQ2_MIF_BOOT_BOOT_STARTED __BIT(24)
+#define AQ2_MIF_BOOT_CRASH_INIT __BIT(27)
+#define AQ2_MIF_BOOT_BOOT_CODE_FAILED __BIT(28)
+#define AQ2_MIF_BOOT_FW_INIT_FAILED __BIT(29)
+#define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS __BIT(31)
+
+/* ART(Action Resolver Table) */
+#define AQ2_ART_ACTION_ACT_MASK __BITS(9,8)
+#define AQ2_ART_ACTION_RSS_MASK __BIT(7)
+#define AQ2_ART_ACTION_INDEX_MASK __BITS(6,2)
+#define AQ2_ART_ACTION_ENABLE_MASK __BIT(0)
+#define AQ2_ART_ACTION(act, rss, idx, en) \
+ (__SHIFTIN((act), AQ2_ART_ACTION_ACT_MASK) | \
+ __SHIFTIN((rss), AQ2_ART_ACTION_RSS_MASK) | \
+ __SHIFTIN((idx), AQ2_ART_ACTION_INDEX_MASK) | \
+ __SHIFTIN((en), AQ2_ART_ACTION_ENABLE_MASK))
+#define AQ2_ART_ACTION_DROP AQ2_ART_ACTION(0, 0, 0, 1)
+#define AQ2_ART_ACTION_DISABLE AQ2_ART_ACTION(0, 0, 0, 0)
+#define AQ2_ART_ACTION_ASSIGN_QUEUE(q) AQ2_ART_ACTION(1, 0, (q), 1)
+#define AQ2_ART_ACTION_ASSIGN_TC(tc) AQ2_ART_ACTION(1, 1, (tc), 1)
+
+#define AQ2_RPF_TAG_PCP_MASK __BITS(31,29)
+#define AQ2_RPF_TAG_FLEX_MASK __BITS(28,27)
+#define AQ2_RPF_TAG_UNKNOWN_MASK __BITS(26,24)
+#define AQ2_RPF_TAG_L4_MASK __BITS(23,21)
+#define AQ2_RPF_TAG_L3_V6_MASK __BITS(20,18)
+#define AQ2_RPF_TAG_L3_V4_MASK __BITS(17,15)
+#define AQ2_RPF_TAG_UNTAG_MASK __BIT(14)
+#define AQ2_RPF_TAG_VLAN_MASK __BITS(13,10)
+#define AQ2_RPF_TAG_ET_MASK __BITS(9,7)
+#define AQ2_RPF_TAG_ALLMC_MASK __BIT(6)
+#define AQ2_RPF_TAG_UC_MASK __BITS(5,0)
+
+/* index of aq2_filter_art_set() */
+#define AQ2_RPF_INDEX_L2_PROMISC_OFF 0
+#define AQ2_RPF_INDEX_VLAN_PROMISC_OFF 1
+#define AQ2_RPF_INDEX_L3L4_USER 8
+#define AQ2_RPF_INDEX_ET_PCP_USER 24
+#define AQ2_RPF_INDEX_VLAN_USER 40
+#define AQ2_RPF_INDEX_PCP_TO_TC 56
+
+#define AQ2_RPF_L2BC_TAG_REG 0x50f0
+#define AQ2_RPF_L2BC_TAG_MASK __BITS(5,0)
+
+#define AQ2_RPF_NEW_CTRL_REG 0x5104
+#define AQ2_RPF_NEW_CTRL_ENABLE __BIT(11)
+
+#define AQ2_RPF_L2UC_TAG_REG(i) (0x5110 + (i) * 8)
+#define AQ2_RPF_L2UC_TAG_MASK __BITS(27,22)
+
+#define AQ2_RPF_REDIR2_REG 0x54c8
+#define AQ2_RPF_REDIR2_INDEX __BIT(12)
+#define AQ2_RPF_REDIR2_HASHTYPE __BITS(8,0)
+#define AQ2_RPF_REDIR2_HASHTYPE_NONE 0
+#define AQ2_RPF_REDIR2_HASHTYPE_IP __BIT(0)
+#define AQ2_RPF_REDIR2_HASHTYPE_TCP4 __BIT(1)
+#define AQ2_RPF_REDIR2_HASHTYPE_UDP4 __BIT(2)
+#define AQ2_RPF_REDIR2_HASHTYPE_IP6 __BIT(3)
+#define AQ2_RPF_REDIR2_HASHTYPE_TCP6 __BIT(4)
+#define AQ2_RPF_REDIR2_HASHTYPE_UDP6 __BIT(5)
+#define AQ2_RPF_REDIR2_HASHTYPE_IP6EX __BIT(6)
+#define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX __BIT(7)
+#define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX __BIT(8)
+#define AQ2_RPF_REDIR2_HASHTYPE_ALL __BITS(8,0)
+
+#define AQ2_RX_Q_TC_MAP_REG(i) (0x5900 + (i) * 4)
+
+#define AQ2_RDM_RX_DESC_RD_REQ_LIMIT_REG 0x5a04
+
+#define AQ2_RPF_RSS_REDIR_REG(tc, i) \
+ (0x6200 + (0x100 * ((tc) >> 2)) + (i) * 4)
+#define AQ2_RPF_RSS_REDIR_TC_MASK(tc) \
+ (__BITS(4,0) << (5 * ((tc) & 3)))
+
+#define AQ2_RPF_L3_V6_V4_SELECT_REG 0x6500
+#define AQ2_RPF_L3_V6_V4_SELECT_EN __BIT(23)
+
+#define AQ2_RPF_REC_TAB_ENABLE_REG 0x6ff0
+#define AQ2_RPF_REC_TAB_ENABLE_MASK __BITS(15,0)
+
+#define AQ2_TX_Q_TC_MAP_REG(i) (0x799c + (i) * 4)
+
+#define AQ2_LAUNCHTIME_CTRL_REG 0x7a1c
+#define AQ2_LAUNCHTIME_CTRL_RATIO __BITS(15,8)
+#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUATER 4
+#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF 2
+#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL 1
+
+/* AT2_TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x7c28-0x8428 */
+#define AQ2_TX_INTR_MODERATION_CTL_REG(i) (0x7c28 + (i) * 0x40)
+#define AQ2_TX_INTR_MODERATION_CTL_EN __BIT(1)
+#define AQ2_TX_INTR_MODERATION_CTL_MIN __BITS(15,8)
+#define AQ2_TX_INTR_MODERATION_CTL_MAX __BITS(24,16)
+
+/* RW shared buffer */
+#define AQ2_FW_INTERFACE_IN_MTU_REG 0x12000
+#define AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG 0x12008
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG 0x12010
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_PROMISCUOUS_MODE __BIT(13)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FRAME_PADDING_REMOVAL_RX __BIT(12)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CRC_FORWARDING __BIT(11)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_TX_PADDING __BIT(10)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CONTROL_FRAME __BIT(9)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_ERROR_FRAME __BIT(8)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_LENGTH_CHECK __BIT(7)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FLOW_CONTROL_MODE __BIT(6)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_SHORT_FRAMES __BIT(5)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_CRC_CORRUPTION __BIT(4)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE __BITS(3,0)
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_INVALID 0
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE 1
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SLEEP_PROXY 2
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_LOWPOWER 3
+#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN 4
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