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[src/netbsd-9]: src/sys/dev/pci Regen for ticket #1566
details: https://anonhg.NetBSD.org/src/rev/ca262a4242de
branches: netbsd-9
changeset: 373103:ca262a4242de
user: martin <martin%NetBSD.org@localhost>
date: Wed Jan 18 19:27:18 2023 +0000
description:
Regen for ticket #1566
diffstat:
sys/dev/pci/pcidevs.h | 131 +-
sys/dev/pci/pcidevs_data.h | 26073 +++++++++++++++++++++---------------------
2 files changed, 13263 insertions(+), 12941 deletions(-)
diffs (truncated from 34661 to 300 lines):
diff -r 94445d49a626 -r ca262a4242de sys/dev/pci/pcidevs.h
--- a/sys/dev/pci/pcidevs.h Wed Jan 18 19:26:30 2023 +0000
+++ b/sys/dev/pci/pcidevs.h Wed Jan 18 19:27:18 2023 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.1371.2.13 2022/10/11 17:51:18 martin Exp $ */
+/* $NetBSD: pcidevs.h,v 1.1371.2.14 2023/01/18 19:27:18 martin Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1383.2.13 2022/10/11 17:49:35 martin Exp
+ * NetBSD: pcidevs,v 1.1383.2.14 2023/01/18 19:26:30 martin Exp
*/
/*
@@ -1035,6 +1035,7 @@
#define PCI_PRODUCT_AMD_F17_PCIE_1 0x1452 /* Family17h PCIe */
#define PCI_PRODUCT_AMD_F17_PCIE_2 0x1453 /* Family17h PCIe */
#define PCI_PRODUCT_AMD_F17_PCIE_3 0x1454 /* Family17h PCIe */
+#define PCI_PRODUCT_AMD_F17_AX_PCIE_DUMMY 0x1455 /* 17h/Axh PCIe Dummy Function */
#define PCI_PRODUCT_AMD_F17_CCP_1 0x1456 /* Family17h Crypto */
#define PCI_PRODUCT_AMD_F17_HDA 0x1457 /* Family17h HD Audio */
#define PCI_PRODUCT_AMD_F17_PCIE_DUMMY 0x145a /* Family17h PCIe Dummy Function */
@@ -1060,7 +1061,43 @@
#define PCI_PRODUCT_AMD_F17_7X_CCP 0x1486 /* Family17h/7xh Crypto */
#define PCI_PRODUCT_AMD_F17_3X_HDA 0x1487 /* 17h/7xh HD Audio */
#define PCI_PRODUCT_AMD_F17_7X_USB3 0x149c /* Family17h/7xh USB 3.0 Host Controller */
+#define PCI_PRODUCT_AMD_F19_1X_IOMMU 0x149e /* 19h/7xh IOMMU */
+#define PCI_PRODUCT_AMD_F19_1X_PCIE_DUMMY_HB 0x149f /* 19h/7xh PCIe Dummy Host Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_RC 0x14a4 /* 19h/1xh Root Complex */
+#define PCI_PRODUCT_AMD_F19_1X_GPPB_0 0x14a5 /* 19h/1xh PCIe GPP Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_RCEC 0x14a6 /* 19h/1xh RCEC */
+#define PCI_PRODUCT_AMD_F19_1X_INTNL_GPPB 0x14a7 /* 19h/1xh Internal PCIe GPP Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_GPPB_1 0x14aa /* 19h/1xh PCIe GPP Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_GPPB_2 0x14ab /* 19h/1xh PCIe GPP Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_PCIE_DUMMY_0 0x14ac /* 19h/1xh PCIe Dummy Function */
+#define PCI_PRODUCT_AMD_F19_1X_DF_0 0x14ad /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_1 0x14ae /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_2 0x14af /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_3 0x14b0 /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_4 0x14b1 /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_5 0x14b2 /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_6 0x14b3 /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F19_1X_DF_7 0x14b4 /* 19h/1xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_RC 0x14b5 /* 17h/Axh Root Complex */
+#define PCI_PRODUCT_AMD_F17_AX_IOMMU 0x14b6 /* 17h/Axh IOMMU */
+#define PCI_PRODUCT_AMD_F17_AX_PCIE_DUMMY_HB 0x14b7 /* 17h/Axh PCIe Dummy Host Bridge */
+#define PCI_PRODUCT_AMD_F17_AX_INTNL_GPPB_0 0x14b9 /* 17h/Axh Internal GPP Bridge 0 */
+#define PCI_PRODUCT_AMD_F17_AX_GPPB 0x14ba /* 17h/Axh PCIe GPP Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_NTB_0 0x14c0 /* 19h/1xh Primary PCIe Non Transparent Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_VNTB 0x14c1 /* 19h/1xh Secondary vNTB */
+#define PCI_PRODUCT_AMD_F19_1X_PCIE_DUMMY_1 0x14c2 /* 19h/1xh PCIe Dummy Function */
+#define PCI_PRODUCT_AMD_F19_1X_NTB_1 0x14c3 /* 19h/1xh PCIe Non Transparent Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_SWDS 0x14c4 /* 19h/1xh Swith NBIF DS */
+#define PCI_PRODUCT_AMD_F19_1X_NVME 0x14c5 /* 19h/1xh NVMe */
+#define PCI_PRODUCT_AMD_F19_1X_SWUS 0x14c6 /* 19h/1xh Swith US in PCIe */
+#define PCI_PRODUCT_AMD_F19_1X_PSP 0x14ca /* 19h/1xh PSP */
+#define PCI_PRODUCT_AMD_F19_1X_ACP 0x14cb /* 19h/1xh ACP */
+#define PCI_PRODUCT_AMD_F19_1X_HDA 0x14cc /* 19h/1xh HD Audio */
#define PCI_PRODUCT_AMD_F19_6X_RC 0x14d8 /* 19h/6xh Root Complex */
+#define PCI_PRODUCT_AMD_F17_AX_XHCI_0 0x1503 /* 17h/Axh USB 3.1 xHCI */
+#define PCI_PRODUCT_AMD_F17_AX_XHCI_1 0x1504 /* 17h/Axh USB 3.1 xHCI */
+#define PCI_PRODUCT_AMD_F17_AX_USB_BIOM 0x1505 /* 17h/Axh Secure USB BIOmetric */
+#define PCI_PRODUCT_AMD_F17_AX_GFX 0x1506 /* 17h/Axh Internal GPU */
#define PCI_PRODUCT_AMD_F14_RC 0x1510 /* Family14h Root Complex */
#define PCI_PRODUCT_AMD_F14_PCIE_1 0x1512 /* Family14h PCIe */
#define PCI_PRODUCT_AMD_F14_PCIE_2 0x1513 /* Family14h PCIe */
@@ -1092,6 +1129,7 @@
#define PCI_PRODUCT_AMD_F15_6X_HB 0x157b /* 15h/6xh Host Bridge */
#define PCI_PRODUCT_AMD_F15_6X_RP 0x157c /* 15h/6xh Root Port */
#define PCI_PRODUCT_AMD_F15_6X_HB_2 0x157d /* 15h/6xh Host Bridge */
+#define PCI_PRODUCT_AMD_F19_1X_XHCI 0x157f /* 19h/1xh USB 3.2 */
#define PCI_PRODUCT_AMD_F16_30_HT 0x1580 /* Family16h HyperTransport Configuration */
#define PCI_PRODUCT_AMD_F16_30_ADDR 0x1581 /* Family16h Address Map Configuration */
#define PCI_PRODUCT_AMD_F16_30_DRAM 0x1582 /* Family16h DRAM Configuration */
@@ -1128,6 +1166,7 @@
#define PCI_PRODUCT_AMD_F15_MISC 0x1603 /* Family15h Miscellaneous Configuration */
#define PCI_PRODUCT_AMD_F15_LINK 0x1604 /* Family15h Link Configuration */
#define PCI_PRODUCT_AMD_F15_NB 0x1605 /* Family15h North Bridge Configuration */
+#define PCI_PRODUCT_AMD_F17_9X_XHCI_1 0x162c /* 17h/9xh xHCI */
#define PCI_PRODUCT_AMD_F17_6X_RC 0x1630 /* 17h/6xh Root Complex */
#define PCI_PRODUCT_AMD_F17_6X_IOMMU 0x1631 /* 17h/6xh IOMMU */
#define PCI_PRODUCT_AMD_F17_6X_HB 0x1632 /* 17h/6xh Host Bridge */
@@ -1136,10 +1175,24 @@
#define PCI_PRODUCT_AMD_F17_6X_PCIE_3 0x1635 /* 17h/6xh PCIe */
#define PCI_PRODUCT_AMD_F17_6X_HDAUDIO 0x1637 /* 17h/6xh HD Audio Controller */
#define PCI_PRODUCT_AMD_F17_6X_XHCI 0x1639 /* 17h/6xh xHCI */
+#define PCI_PRODUCT_AMD_F17_9X_XHCI_2 0x163b /* 17h/9xh xHCI */
+#define PCI_PRODUCT_AMD_F17_AX_HDA 0x1640 /* 17h/Axh HD Audio */
#define PCI_PRODUCT_AMD_F17_6X_XGBE 0x1641 /* 17h/6xh 10GbE Controller */
#define PCI_PRODUCT_AMD_F17_6X_WLAN 0x1642 /* 17h/6xh WLAN */
#define PCI_PRODUCT_AMD_F17_6X_BT 0x1643 /* 17h/6xh Bluetooth */
#define PCI_PRODUCT_AMD_F17_6X_I2S 0x1644 /* 17h/6xh I2S */
+#define PCI_PRODUCT_AMD_F17_9X_HB 0x1645 /* 17h/9xh Host */
+#define PCI_PRODUCT_AMD_F17_9X_PCIE_1 0x1647 /* 17h/9xh PCIE */
+#define PCI_PRODUCT_AMD_F17_9X_PCIE_2 0x1648 /* 17h/9xh PCIE */
+#define PCI_PRODUCT_AMD_F17_9X_CCP 0x1649 /* 17h/9xh Crypto */
+#define PCI_PRODUCT_AMD_F17_9X_DF_0 0x1660 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_1 0x1661 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_2 0x1662 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_3 0x1663 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_4 0x1664 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_5 0x1665 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_6 0x1666 /* 17h/9xh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_9X_DF_7 0x1667 /* 17h/9xh Data Fabric */
#define PCI_PRODUCT_AMD_F19_5X_DF_0 0x166a /* 19h/5xh Data Fabric */
#define PCI_PRODUCT_AMD_F19_5X_DF_1 0x166b /* 19h/5xh Data Fabric */
#define PCI_PRODUCT_AMD_F19_5X_DF_2 0x166c /* 19h/5xh Data Fabric */
@@ -1164,6 +1217,14 @@
#define PCI_PRODUCT_AMD_F14_MISC 0x1716 /* Family12h/14h Misc. Configuration */
#define PCI_PRODUCT_AMD_F14_HB18 0x1718 /* Family12h/14h Host Bridge */
#define PCI_PRODUCT_AMD_F14_HB19 0x1719 /* Family12h/14h Host Bridge */
+#define PCI_PRODUCT_AMD_F17_AX_DF_0 0x1724 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_1 0x1725 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_2 0x1726 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_3 0x1727 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_4 0x1728 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_5 0x1729 /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_6 0x172a /* 17h/Axh Data Fabric */
+#define PCI_PRODUCT_AMD_F17_AX_DF_7 0x172b /* 17h/Axh Data Fabric */
#define PCI_PRODUCT_AMD_SEATTLE_PCHB_1 0x1a00 /* Seattle Host Bridge */
#define PCI_PRODUCT_AMD_SEATTLE_PCHB_2 0x1a01 /* Seattle Host Bridge */
#define PCI_PRODUCT_AMD_SEATTLE_PCIE 0x1a02 /* Seattle PCIe Root Port */
@@ -1378,17 +1439,25 @@
/* Aquantia Corp. */
#define PCI_PRODUCT_AQUANTIA_AQC100 0x00b1 /* AQC100 10 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC113DEV 0x00c0 /* AQC113DEV 10 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC113 0x04c0 /* AQC113 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC107 0x07b1 /* AQC107 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC108 0x08b1 /* AQC108 5 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC109 0x09b1 /* AQC109 2.5 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC111 0x11b1 /* AQC111 5 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC116C 0x11c0 /* AQC116C Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC112 0x12b1 /* AQC112 2.5 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC115C 0x12c0 /* AQC115C 2.5 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC113C 0x14c0 /* AQC113C 10 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC113CA 0x34c0 /* AQC113CA 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC100S 0x80b1 /* AQC100S 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC107S 0x87b1 /* AQC107S 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC108S 0x88b1 /* AQC108S 5 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC109S 0x89b1 /* AQC109S 2.5 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC111S 0x91b1 /* AQC111S 5 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_AQC112S 0x92b1 /* AQC112S 2.5 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC114CS 0x93c0 /* AQC114CS 5 Gigabit Network Adapter */
+#define PCI_PRODUCT_AQUANTIA_AQC113CS 0x94c0 /* AQC113CS 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_D100 0xd100 /* D100 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_D107 0xd107 /* D107 10 Gigabit Network Adapter */
#define PCI_PRODUCT_AQUANTIA_D108 0xd108 /* D108 5 Gigabit Network Adapter */
@@ -4573,17 +4642,23 @@
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_1 0x2015 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_2 0x2016 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_M2PCIR 0x2018 /* Xeon Scalable M2PCI */
+#define PCI_PRODUCT_INTEL_XEONSC_HB 0x2020 /* Xeon Scalable Host */
#define PCI_PRODUCT_INTEL_XEONSC_CBDMAR 0x2021 /* Xeon Scalable CBDMA */
#define PCI_PRODUCT_INTEL_XEONSC_MMVTD 0x2024 /* Xeon Scalable MM/Vt-d */
#define PCI_PRODUCT_INTEL_XEONSC_RAS 0x2025 /* Xeon Scalable RAS */
#define PCI_PRODUCT_INTEL_XEONSC_IOAPIC 0x2026 /* Xeon Scalable I/O APIC */
+#define PCI_PRODUCT_INTEL_XEONSC_PCIE_1 0x2030 /* Xeon Scalable PCIe */
+#define PCI_PRODUCT_INTEL_XEONSC_PCIE_2 0x2031 /* Xeon Scalable PCIe */
+#define PCI_PRODUCT_INTEL_XEONSC_PCIE_3 0x2032 /* Xeon Scalable PCIe */
+#define PCI_PRODUCT_INTEL_XEONSC_PCIE_4 0x2033 /* Xeon Scalable PCIe */
#define PCI_PRODUCT_INTEL_XEONSC_VTD 0x2034 /* Xeon Scalable VT-d */
#define PCI_PRODUCT_INTEL_XEONSC_RAS_CFG 0x2035 /* Xeon Scalable RAS Configuration */
#define PCI_PRODUCT_INTEL_XEONSC_IOAPIC_C 0x2036 /* Xeon Scalable IOxAPIC */
-#define PCI_PRODUCT_INTEL_XEONSC_IMC_1 0x2041 /* Xeon Scalable IMC */
-#define PCI_PRODUCT_INTEL_XEONSC_IMC_2 0x2042 /* Xeon Scalable IMC */
-#define PCI_PRODUCT_INTEL_XEONSC_IMC_3 0x2043 /* Xeon Scalable IMC */
-#define PCI_PRODUCT_INTEL_XEONSC_IMC_4 0x2044 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC_1 0x2040 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC_2 0x2041 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC_3 0x2042 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC_4 0x2043 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC_5 0x2044 /* Xeon Scalable IMC */
#define PCI_PRODUCT_INTEL_XEONSC_LMC_1 0x2045 /* Xeon Scalable LM */
#define PCI_PRODUCT_INTEL_XEONSC_LMSC_1 0x2046 /* Xeon Scalable LMS */
#define PCI_PRODUCT_INTEL_XEONSC_LMDPC_1 0x2047 /* Xeon Scalable LMDP */
@@ -4593,15 +4668,29 @@
#define PCI_PRODUCT_INTEL_XEONSC_LMDPC_2 0x204b /* Xeon Scalable LMDP */
#define PCI_PRODUCT_INTEL_XEONSC_M3KTI_1 0x204c /* Xeon Scalable M3KTI */
#define PCI_PRODUCT_INTEL_XEONSC_M3KTI_2 0x204d /* Xeon Scalable M3KTI */
+#define PCI_PRODUCT_INTEL_XEONSC_M3KTI_3 0x204e /* Xeon Scalable M3KTI */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_1 0x2054 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_2 0x2055 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_3 0x2056 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_4 0x2057 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_KTI 0x2058 /* Xeon Scalable KTI */
#define PCI_PRODUCT_INTEL_XEONSC_UPIR 0x2059 /* Xeon Scalable UPI */
-#define PCI_PRODUCT_INTEL_XEONSC_PCU_0 0x2080 /* Xeon Scalable PCU */
-#define PCI_PRODUCT_INTEL_XEONSC_PCU_1 0x2081 /* Xeon Scalable PCU */
-#define PCI_PRODUCT_INTEL_XEONSC_PCU_2 0x2082 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_IMC 0x2066 /* Xeon Scalable IMC */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_1 0x2068 /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_2 0x2069 /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_3 0x206a /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_4 0x206b /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_5 0x206c /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_6 0x206d /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_DDRIO_7 0x206e /* Xeon Scalable DDRIO */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_1 0x2080 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_2 0x2081 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_3 0x2082 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_4 0x2083 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_5 0x2084 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_6 0x2085 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_7 0x2086 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_M2PCIE 0x2088 /* Xeon Scalable M2PCIe */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_5 0x208d /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_6 0x208e /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_BSW_HB 0x2280 /* Braswell Soc Transaction Router */
@@ -4614,9 +4703,9 @@
#define PCI_PRODUCT_INTEL_Z8K_LPIO1_SPI_1 0x228e /* Atom Z8000 LPIO1 SPI1 */
#define PCI_PRODUCT_INTEL_Z8K_LPIO1_SPI_2 0x2290 /* Atom Z8000 LPIO1 SPI2 */
#define PCI_PRODUCT_INTEL_BSW_PCU_SMB 0x2292 /* Braswell PCU SMBus */
-#define PCI_PRODUCT_INTEL_BSW_SSC_MMC 0x2294 /* Braswell SCC MMC Port */
-#define PCI_PRODUCT_INTEL_BSW_SSC_SDIO 0x2295 /* Braswell SCC SDIO Port */
-#define PCI_PRODUCT_INTEL_BSW_SSC_SD 0x2296 /* Braswell SCC SD Port */
+#define PCI_PRODUCT_INTEL_BSW_SCC_MMC 0x2294 /* Braswell SCC MMC Port */
+#define PCI_PRODUCT_INTEL_BSW_SCC_SDIO 0x2295 /* Braswell SCC SDIO Port */
+#define PCI_PRODUCT_INTEL_BSW_SCC_SD 0x2296 /* Braswell SCC SD Port */
#define PCI_PRODUCT_INTEL_BSW_TXE 0x2298 /* Braswell TXE */
#define PCI_PRODUCT_INTEL_BSW_PCU_LPC 0x229c /* Braswell PCU LPC */
#define PCI_PRODUCT_INTEL_BSW_AHCI 0x22a3 /* Braswell AHCI */
@@ -5736,25 +5825,33 @@
#define PCI_PRODUCT_INTEL_5HS_H_ISH 0x43fc /* 500 Series PCH-H Integrated Sensor Hub */
#define PCI_PRODUCT_INTEL_5HS_H_GSPI_3 0x43fd /* 500 Series PCH-H GSPI 3 */
#define PCI_PRODUCT_INTEL_EHL_DPTF 0x4503 /* Elkhart Lake DPTF */
+#define PCI_PRODUCT_INTEL_EHL_TROUTER_2C_S 0x4510 /* Elkhart Lake Transaction Router (2C, Super SKU) */
#define PCI_PRODUCT_INTEL_EHL_GNA 0x4511 /* Elkhart Lake GNA */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_3 0x4512 /* Elkhart Lake Transaction Router (SKU 3) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_5 0x4514 /* Elkhart Lake Transaction Router (SKU 5) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_8 0x4516 /* Elkhart Lake Transaction Router (SKU 8) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_12 0x4518 /* Elkhart Lake Transaction Router (SKU 12) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_3A 0x451e /* Elkhart Lake Transaction Router (SKU 3A) */
+#define PCI_PRODUCT_INTEL_EHL_TROUTER_4C_S 0x4520 /* Elkhart Lake Transaction Router (4C, Super SKU) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_1 0x4522 /* Elkhart Lake Transaction Router (SKU 1) */
+#define PCI_PRODUCT_INTEL_EHL_TROUTER_2_PREQS 0x4524 /* Elkhart Lake Transaction Router (SKU 2, pre-QS) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_4 0x4526 /* Elkhart Lake Transaction Router (SKU 4) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_6 0x4528 /* Elkhart Lake Transaction Router (SKU 6) */
#define PCI_PRODUCT_INTEL_EHL_TRACE_2 0x4529 /* Elkhart Lake Trace Hub (Compute Die) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_7 0x452a /* Elkhart Lake Transaction Router (SKU 7) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_9 0x452c /* Elkhart Lake Transaction Router (SKU 9) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_10 0x452e /* Elkhart Lake Transaction Router (SKU 10) */
+#define PCI_PRODUCT_INTEL_EHL_TROUTER_4C_S_2 0x4530 /* Elkhart Lake Transaction Router (4C, Super SKU) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_11 0x4532 /* Elkhart Lake Transaction Router (SKU 11) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_1A 0x4538 /* Elkhart Lake Transaction Router (SKU 1A) */
#define PCI_PRODUCT_INTEL_EHL_TROUTER_2 0x453a /* Elkhart Lake Transaction Router (SKU 2) */
-#define PCI_PRODUCT_INTEL_EHL_GPU_16 0x4551 /* Elkhart Lake GPU (16EU) */
-#define PCI_PRODUCT_INTEL_EHL_GPU_32_SUPER 0x4551 /* Elkhart Lake GPU (32EU Super) */
-#define PCI_PRODUCT_INTEL_EHL_GPU_32 0x4551 /* Elkhart Lake GPU (32EU) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_8EU_S 0x4540 /* Elkhart Lake GPU (8EU Super) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_8EU 0x4541 /* Elkhart Lake GPU (8EU Super) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_16EU_S 0x4550 /* Elkhart Lake GPU (16EU Super) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_16EU_OLD 0x4551 /* Elkhart Lake GPU (16EU) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_16EU 0x4555 /* Elkhart Lake GPU (16EU) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_32_S 0x4570 /* Elkhart Lake GPU (32EU Super) */
+#define PCI_PRODUCT_INTEL_EHL_GPU_32 0x4571 /* Elkhart Lake GPU (32EU) */
#define PCI_PRODUCT_INTEL_ADL_U15_2_8_HOST 0x4601 /* Alder Lake (U15,2+8) Host */
#define PCI_PRODUCT_INTEL_ADL_U9_2_8_HOST 0x4602 /* Alder Lake (U9,2+8) Host */
#define PCI_PRODUCT_INTEL_ADL_U15_2_4_HOST 0x4609 /* Alder Lake (U15,2+4) Host */
@@ -5843,6 +5940,7 @@
#define PCI_PRODUCT_INTEL_EHL_CAVS_7 0x4b5b /* Elkhart Lake cAVS */
#define PCI_PRODUCT_INTEL_EHL_CAVS_8 0x4b5c /* Elkhart Lake cAVS */
#define PCI_PRODUCT_INTEL_EHL_AHCI 0x4b60 /* Elkhart Lake AHCI */
+#define PCI_PRODUCT_INTEL_EHL_AHCI_2 0x4b63 /* Elkhart Lake AHCI */
#define PCI_PRODUCT_INTEL_EHL_HPET 0x4b68 /* Elkhart Lake HPET */
#define PCI_PRODUCT_INTEL_EHL_IOAPIC 0x4b69 /* Elkhart Lake IOAPIC */
#define PCI_PRODUCT_INTEL_EHL_CSE_PTTDMA 0x4b6b /* Elkhart Lake CSE PTT DMA */
@@ -5857,6 +5955,7 @@
#define PCI_PRODUCT_INTEL_EHL_SIO_I2C_3 0x4b7b /* Elkhart Lake SIO I2C 3 */
#define PCI_PRODUCT_INTEL_EHL_XHCI 0x4b7d /* Elkhart Lake xHCI */
#define PCI_PRODUCT_INTEL_EHL_XDCI 0x4b7e /* Elkhart Lake xDCI */
+#define PCI_PRODUCT_INTEL_EHL_SSRAM 0x4b7f /* Elkhart Lake Shared SRAM */
#define PCI_PRODUCT_INTEL_EHL_PSE_QEP_1 0x4b81 /* Elkhart Lake PSE QEP 1 */
#define PCI_PRODUCT_INTEL_EHL_PSE_QEP_2 0x4b82 /* Elkhart Lake PSE QEP 2 */
#define PCI_PRODUCT_INTEL_EHL_PSE_QEP_3 0x4b83 /* Elkhart Lake PSE QEP 3 */
@@ -5879,7 +5978,7 @@
#define PCI_PRODUCT_INTEL_EHL_PSE_ETH_0_SGMII_2_5G 0x4ba2 /* Elkhart Lake PSE Ethernet 0 (SGMII 2.5G) */
#define PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_RGMII 0x4bb0 /* Elkhart Lake PSE Ethernet 1 (RGMII 1G) */
#define PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_SGMII_1G 0x4bb1 /* Elkhart Lake PSE Ethernet 1 (SGMII 1G) */
-#define PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_SGMII_2_5G 0x4bb2 /* Elkhart Lake PSE Ethernet 1 (SGMII 1G) */
+#define PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_SGMII_2_5G 0x4bb2 /* Elkhart Lake PSE Ethernet 1 (SGMII 2.5G) */
#define PCI_PRODUCT_INTEL_EHL_PSE_LH2OSE 0x4bb3 /* Elkhart Lake PSE LH2OSE */
#define PCI_PRODUCT_INTEL_EHL_PSE_DMA_0 0x4bb4 /* Elkhart Lake PSE DMA 0 */
#define PCI_PRODUCT_INTEL_EHL_PSE_DMA_1 0x4bb5 /* Elkhart Lake PSE DMA 1 */
diff -r 94445d49a626 -r ca262a4242de sys/dev/pci/pcidevs_data.h
--- a/sys/dev/pci/pcidevs_data.h Wed Jan 18 19:26:30 2023 +0000
+++ b/sys/dev/pci/pcidevs_data.h Wed Jan 18 19:27:18 2023 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs_data.h,v 1.1370.2.13 2022/10/11 17:51:18 martin Exp $ */
+/* $NetBSD: pcidevs_data.h,v 1.1370.2.14 2023/01/18 19:27:18 martin Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1383.2.13 2022/10/11 17:49:35 martin Exp
+ * NetBSD: pcidevs,v 1.1383.2.14 2023/01/18 19:26:30 martin Exp
*/
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