[src/trunk]: src/sys/arch/x86/pci Reduce diff against DragonFly. No functiona...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a1b4d88542d6
branches:  trunk
changeset: 373264:a1b4d88542d6
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Sat Jan 28 07:45:21 2023 +0000

description:
Reduce diff against DragonFly. No functional change.

diffstat:

 sys/arch/x86/pci/amdzentemp.c |  33 ++++++++++++++-------------------
 1 files changed, 14 insertions(+), 19 deletions(-)

diffs (112 lines):

diff -r 3c15490a2ae7 -r a1b4d88542d6 sys/arch/x86/pci/amdzentemp.c
--- a/sys/arch/x86/pci/amdzentemp.c     Sat Jan 28 05:25:17 2023 +0000
+++ b/sys/arch/x86/pci/amdzentemp.c     Sat Jan 28 07:45:21 2023 +0000
@@ -1,4 +1,4 @@
-/*      $NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ */
+/*      $NetBSD: amdzentemp.c,v 1.17 2023/01/28 07:45:21 msaitoh Exp $ */
 /*      $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $   */
 
 /*
@@ -53,7 +53,7 @@
 
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.17 2023/01/28 07:45:21 msaitoh Exp $ ");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -74,7 +74,6 @@
 #include "amdsmn.h"
 
 #define        AMD_CURTMP_RANGE_ADJUST 49000000        /* in microKelvins (ie, 49C) */
-#define        AMD_CURTMP_RANGE_CHECK  __BIT(19)
 #define        F10_TEMP_CURTMP         __BITS(31,21)   /* XXX same as amdtemp.c */
 #define        F10_TEMP_CURTMP_MASK    0x7ff
 #define        F15M60_CURTMP_TJSEL     __BITS(17,16)
@@ -96,14 +95,7 @@
  * to -49..206C.
  */
 #define        AMD_17H_CUR_TMP                 0x59800
-
-/*
- * The following register set was discovered experimentally by Ondrej Čerman
- * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
- * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
- * SMU::THM).  It seems plausible and the Linux sensor folks have adopted it.
- */
-#define        AMD_17H_CCD_TMP_BASE            0x59954
+#define        AMD_17H_CUR_TMP_RANGE_SEL       __BIT(19)
 #define        AMD_17H_CCD_TMP_VALID           __BIT(11)
 
 struct amdzentemp_softc {
@@ -114,7 +106,7 @@
        size_t sc_sensor_len;
        size_t sc_numsensors;
        int32_t sc_offset;
-       uint32_t sc_ccd_tmp_base;
+       int32_t sc_ccd_offset;
 };
 
 enum {
@@ -339,14 +331,16 @@
                        edata->state = ENVSYS_SINVALID;
                        return;
                }
-               minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
+               minus49 = (temp & AMD_17H_CUR_TMP_RANGE_SEL) ?
+                   true : false;
                temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
                break;
        case CCD_BASE ... (CCD_MAX - 1):
                /* Tccd */
                i = edata->private - CCD_BASE;
                error = amdsmn_read(sc->sc_smn,
-                   sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
+                   AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+                   &temp);
                if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
                        edata->state = ENVSYS_SINVALID;
                        return;
@@ -372,6 +366,8 @@
 {
        int maxreg;
 
+       sc->sc_ccd_offset = 0x154;
+
        switch (model) {
        case 0x00 ... 0x2f: /* Zen1, Zen+ */
                maxreg = 4;
@@ -399,10 +395,11 @@
        case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
        case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
        case 0x50 ... 0x5f: /* Zen3 Ryzen "Cezanne" */
+               sc->sc_ccd_offset = 0x154;
                maxreg = 8;
                break;
        case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
-               sc->sc_ccd_tmp_base = 0x59b08;
+               sc->sc_ccd_offset = 0x308;
                maxreg = 8;
                break;
        default:
@@ -419,9 +416,6 @@
 {
        int nccd;
 
-       /* Set default CCD temp sensor base address. */
-       sc->sc_ccd_tmp_base = 0x59954;
-
        switch (family) {
        case 0x17:
                nccd = amdzentemp_probe_ccd_sensors17h(sc, model);
@@ -446,7 +440,8 @@
 
        for (i = 0; i < sc->sc_numsensors - 1; i++) {
                error = amdsmn_read(sc->sc_smn,
-                   sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
+                   AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+                   &temp);
                if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID))
                        continue;