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[src-draft/trunk]: src/sys/dev/usb For delays greater than 1ms use urtwn_dela...
details: https://anonhg.NetBSD.org/src-all/rev/f669c1ac49ab
branches: trunk
changeset: 377722:f669c1ac49ab
user: Nathanial Sloss <nat%netbsd.org@localhost>
date: Sat Jun 20 08:30:12 2020 +1000
description:
For delays greater than 1ms use urtwn_delay. NFCI.
diffstat:
sys/dev/usb/if_urtwn.c | 152 ++++++++++++++++++++++++------------------------
1 files changed, 76 insertions(+), 76 deletions(-)
diffs (truncated from 545 to 300 lines):
diff -r f44180792265 -r f669c1ac49ab sys/dev/usb/if_urtwn.c
--- a/sys/dev/usb/if_urtwn.c Sat Jun 20 08:29:05 2020 +1000
+++ b/sys/dev/usb/if_urtwn.c Sat Jun 20 08:30:12 2020 +1000
@@ -1212,7 +1212,7 @@ urtwn_fw_cmd(struct urtwn_softc *sc, uin
for (ntries = 0; ntries < 100; ntries++) {
if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur)))
break;
- DELAY(2000);
+ urtwn_delay_ms(sc, 2);
}
if (ntries == 100) {
aprint_error_dev(sc->sc_dev,
@@ -1263,7 +1263,7 @@ urtwn_r92c_rf_write(struct urtwn_softc *
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
static void
@@ -1273,7 +1273,7 @@ urtwn_r88e_rf_write(struct urtwn_softc *
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
static void
@@ -1283,7 +1283,7 @@ urtwn_r92e_rf_write(struct urtwn_softc *
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
static uint32_t
@@ -1298,16 +1298,16 @@ urtwn_rf_read(struct urtwn_softc *sc, in
urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
R92C_HSSI_PARAM2_READ_EDGE);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) {
val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
@@ -2358,7 +2358,7 @@ urtwn_newstate(struct ieee80211vap *vap,
callout_stop(&sc->sc_scan_to);
callout_stop(&sc->sc_calib_to);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
switch (ostate) {
case IEEE80211_S_INIT:
@@ -2415,7 +2415,7 @@ urtwn_newstate(struct ieee80211vap *vap,
urtwn_read_1(sc, R92C_BCN_CTRL) &
~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT));
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Reset EDCA parameters. */
urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
@@ -2434,7 +2434,7 @@ urtwn_newstate(struct ieee80211vap *vap,
break;
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
switch (nstate) {
case IEEE80211_S_INIT:
@@ -2461,7 +2461,7 @@ urtwn_newstate(struct ieee80211vap *vap,
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Set media status to 'No Link'. */
urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -2479,7 +2479,7 @@ urtwn_newstate(struct ieee80211vap *vap,
R92C_BCN_CTRL_DIS_TSF_UDT0);
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Make link LED blink during scan. */
urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
@@ -2505,13 +2505,13 @@ urtwn_newstate(struct ieee80211vap *vap,
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Set media status to 'No Link'. */
urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -2569,7 +2569,7 @@ urtwn_newstate(struct ieee80211vap *vap,
break;
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Set media status to 'Associated'. */
urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc));
@@ -2585,7 +2585,7 @@ urtwn_newstate(struct ieee80211vap *vap,
} else /* IEEE_MODE_11NG */
urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Enable Rx of data frames. */
urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
@@ -4404,7 +4404,7 @@ urtwn_load_firmware(struct urtwn_softc *
error = ETIMEDOUT;
goto fail;
}
- DELAY(10000);
+ urtwn_delay_ms(sc, 10);
fail:
firmware_free(fw, fwlen);
return error;
@@ -4674,48 +4674,48 @@ urtwn_bb_init(struct urtwn_softc *sc)
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
reg = (reg & ~0x00000003) | 0x2;
urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
reg = (reg & ~0x00300033) | 0x00200022;
urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
reg = (reg & ~0xff000000) | (0x45 << 24);
urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg = (reg & ~0x000000ff) | 0x23;
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
reg = (reg & ~0x00000030) | (1 << 4);
urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe74);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe74, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe78);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe78, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe7c);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe7c, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe80);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe80, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe88);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe88, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
/* Write AGC values. */
@@ -4741,7 +4741,7 @@ urtwn_bb_init(struct urtwn_softc *sc)
urtwn_bb_write(sc, R92C_AFE_CTRL3,
RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
crystalcap | crystalcap << 6));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb);
} else if (ISSET(sc->chip, URTWN_CHIP_88E)) {
crystalcap = sc->r88e_rom[0xb9];
@@ -4752,14 +4752,14 @@ urtwn_bb_init(struct urtwn_softc *sc)
urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
crystalcap | crystalcap << 6));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
} else {
if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
R92C_HSSI_PARAM2_CCK_HIPWR) {
SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR);
}
}
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
static void __noinline
@@ -4834,7 +4834,7 @@ urtwn_rf_init(struct urtwn_softc *sc)
/* Restore RF_ENV control type. */
reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
@@ -4987,26 +4987,26 @@ urtwn_write_txpower(struct urtwn_softc *
reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
} else {
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
}
/* Write per-OFDM rate Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
@@ -5014,38 +5014,38 @@ urtwn_write_txpower(struct urtwn_softc *
SM(R92C_TXAGC_RATE09, power[ 5]) |
SM(R92C_TXAGC_RATE12, power[ 6]) |
SM(R92C_TXAGC_RATE18, power[ 7]));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
SM(R92C_TXAGC_RATE24, power[ 8]) |
SM(R92C_TXAGC_RATE36, power[ 9]) |
SM(R92C_TXAGC_RATE48, power[10]) |
SM(R92C_TXAGC_RATE54, power[11]));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
/* Write per-MCS Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
SM(R92C_TXAGC_MCS00, power[12]) |
SM(R92C_TXAGC_MCS01, power[13]) |
SM(R92C_TXAGC_MCS02, power[14]) |
SM(R92C_TXAGC_MCS03, power[15]));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
SM(R92C_TXAGC_MCS04, power[16]) |
SM(R92C_TXAGC_MCS05, power[17]) |
SM(R92C_TXAGC_MCS06, power[18]) |
SM(R92C_TXAGC_MCS07, power[19]));
- DELAY(1000);
+ urtwn_delay_ms(sc, 1);
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