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CVS commit: src



Module Name:    src
Committed By:   castor
Date:           Fri Jan 29 16:10:07 UTC 1999

Modified Files:
        src/sys/arch/mips/mips: locore_mips3.S
Log Message:
Copy previous fix for TLB miss routine to XTLB miss routine to avoid
processor-dependent behavior in 32-bit ops on 64-bit operands.




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