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CVS commit: src



Module Name:    src
Committed By:   jonathan
Date:           Tue Feb 16 10:10:51 UTC 1999

Modified Files:
        src/sys/arch/mips/mips: mips_mcclock.c
Log Message:
Bump mips3 CPU-mhz timing threshholds by 10% due to egcs wins.
XXX mips1 not recalibrated.




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