CVS commit: src

[Tohru Nishimura <nisimura%netbsd.org@localhost>]

Module Name:    src
Committed By:   nisimura
Date:           Fri May  7 01:30:28 UTC 1999

Modified Files:
        src/sys/arch/mips/mips: locore.S
Log Message:
- Introduce MIPS processor interrupt control routines;
_splraise, _spllower, _splset, _splget, _setsoftintr, _clrsoftintr, _splnone.

They manipulate MIPS processor's 8 interrupt sources and are used
as building blocks for NetBSD spl(9) kernel interface.  Note that
MIPS processor doesn't enforce inclusive 'interrupt levels' found
in other processors, then the hierarchal nature of IPL must be
implemented by composing MIPS processor interrupt masks appropriately.

With the simplest target port in which small number of devices are
independently assigned with 6 external interrupt signal lines,
spl(9) kernel interface will be implemented with #define's of
processor interrupt controls mentioned above.  In more general
cases, in which target computers have many devices and 'system
registers' indicating pending interrupt sources at any moment,
spl(9) will be implemented with more complex machinary manipulating
processor interrupts and system registers in target port dependent
ways.

- Nuke unused code and reorder locore definitions.  XXX Following
routines will be replaced with C language version; setrunqueue,
remrunqueue, switchfpregs, savefpregs, MachFPInterrupt.