CVS commit: syssrc

["Michael L. Hitch" <mhitch%netbsd.org@localhost>]

Module Name:    syssrc
Committed By:   mhitch
Date:           Wed Feb 23 17:04:07 UTC 2000

Modified Files:
        syssrc/sys/arch/mips/mips: locore_mips1.S

Log Message:
Loading the exception return PC in k0 before restoring the status register
(which disables the interrupts) is *not* a good idea.  k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.


To generate a diff of this commit:
cvs rdiff -r1.21 -r1.22 syssrc/sys/arch/mips/mips/locore_mips1.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.