Re: uvm_pageidlezero() on mips

["Michael L. Hitch" <mhitch%lightning.msu.montana.edu@localhost>]

On Mon, 1 May 2000, Simon Burge wrote:

> "Michael L. Hitch" wrote:
> 
> >   This fails miserably on my 5000/25.  Trying to run programs get segment
> > violations very frequently.  My guess at this point is that using
> > uncached address space to zero the page leaves non-zeroed data in the
> > cache.  If that cached data is then used instead of the zeroed memory,
> > things that expect the data to be zero will fail.
> 
> Works ok for me on an r4400 - maybe it's a MIPS1/MIPS3 thang?  If so,
> maybe we just put

  The MIPS3 might catch problems with the virtual coherencey checks,
although I can't think of how that might work.  When the memory is zeroed
using the KSEG1 address, it wouldn't touch the L1 or L2 cache, and they
could still contain stale data.  If any of that data was 'dirty', and
a later cache miss occurred, then the stale data would get written to
memory - which I would think would eventually cause some noticable
problem.  I suppose that it's possible that the MIPS3 cache flushing
process may not leave any stale data sitting in the cache, but I can't
think of any case where this would happen.

--
Michael L. Hitch                        mhitch%montana.edu@localhost
Computer Consultant
Information Technology Center
Montana State University        Bozeman, MT     USA