CVS commit: pkgsrc

[Dan McMahill <dmcmahill%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   dmcmahill
Date:           Tue May 30 23:43:45 UTC 2000

Modified Files:
        pkgsrc/cad/verilog-current: Makefile
        pkgsrc/cad/verilog-current/files: md5 patch-sum
        pkgsrc/cad/verilog-current/patches: patch-aa

Log Message:
update to verilog-current-20000527

changes since last packaged snapshot are (from the authors announcements):

Icarus Verilog 20000527 Snapshot
----------------------------------

It's snapshot time!

    <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000527.tar.gz>

This snapshot doesn't add any new features, but fixes a few bugs. I've
taken care of a bunch of bug reports with an eye towards getting this
polished up for a 0.3 stable release.

I fixed some problems with elaborating the condition expression of a
ternary operator. This was a long-standing bug that only happened in
structural (i.e. continuous assignment) situations.

I've also done some merging of event expressions. The netlist format makes
NetEvProbe and NetEvent objects for event expressions, and it was making
more then were needed. I've done some merging, though I have some more
things I can do on this front. I'll be working on it for the next snapshot.

I found a whole bunch of bugs with parsing expression lists, for example
module port expressions. The result is actually a smaller parser:-) So
module port expressions should be parsed and elaborated correctly, now.

In the vvm code generator, I've found some room to optimize the generated
code. I detect duplicate initialization of a nexus, and prevent the
excess code being generating. In one slightly degenerate example sent to
me, this change reduced the generated C++ by more then 6 times. I was
pretty amazed.

I've also slightly optimized the special case of behavioral assignments
from simple signal expressions. This removed a few lines of generated
code per assignment. This sort of thing helps compile time performance.

Icarus Verilog 20000512 Snapshot
----------------------------------
This is mostly a bug fix snapshot. No new features here, but I'm starting
to buff it up shiny for an upcoming 0.3 release. It looks like I'll be
starting to do release candidates soon, so test this snapshot hard, folks!

    <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000519.tar.gz>

I re-implemented flip-flop and RAM synthesis, the new technique should
allow me to make much more complete synthesis. It's still not the nifty
full-scale synthesis I hope to do some day, but it should catch some of
the bigger synthesis problems.

I've also added to XNF synthesis the ability to detect start-up initial
values for flip-flip devices. This causes it to generate INIT= properties
for the devices as appropriate.

I've improved the VVM code generated by the t-vvm code generator. I've
managed to reduce the size of the code generated for some larger models
by 30%, and I should have improved run-time performance in the process.
This should help.

I've also found (thanks to bug reports) and fixed some module port issues.
I bet you can't dream up legal port binding that Icarus Verilog can't
handle:-) This issue should be taken care of.

VPI now includes the ability to set registers. I needed this to implement
a PNG image I/O module. I'm still working on that, I'll distribute it
separately when it is in better shape.

Various other bug fixes in iverilog and elsewhere. Several bug fixes
in the VVM runtime, including some support for the % operator.

I've done some updates to documentation to reflect some of the changes
since 0.2, so you can take a look at that too.


To generate a diff of this commit:
cvs rdiff -r1.5 -r1.6 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.5 -r1.6 pkgsrc/cad/verilog-current/files/md5 \
    pkgsrc/cad/verilog-current/files/patch-sum
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/verilog-current/patches/patch-aa

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.