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CVS commit: src/sys/arch/cobalt/dev
Module Name: src
Committed By: tsutsui
Date: Sun Apr 16 05:11:08 UTC 2006
Modified Files:
src/sys/arch/cobalt/dev: gt.c
Log Message:
Pass mips_dcache_align to pci_configure_bus(9) for cacheline_size.
To generate a diff of this commit:
cvs rdiff -r1.15 -r1.16 src/sys/arch/cobalt/dev/gt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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