CVS commit: src/sys/arch/x86/x86

[Joerg Sonnenberger <joerg%netbsd.org@localhost>]

Module Name:    src
Committed By:   joerg
Date:           Wed Oct 24 06:21:32 UTC 2007

Modified Files:
        src/sys/arch/x86/x86: est.c

Log Message:
Before faking up a state table, make sure that neither frequency nor
voltage difference is 0. This avoids a divide by zero.


To generate a diff of this commit:
cvs rdiff -r1.3 -r1.4 src/sys/arch/x86/x86/est.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.