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CVS commit: src/sys/arch/i386/i386
Module Name: src
Committed By: dsl
Date: Sun Jan 10 15:21:36 UTC 2010
Modified Files:
src/sys/arch/i386/i386: trap.c vector.S
Log Message:
If we fault on the 'iret' during return to userpace (eg if %eip is outside
the bounds of %cs) then hack the stack to contain a normal fault frame
for the signal setup code (etc).
Previously the code assumed that the original user trap frame was still
present - at it is for faults when loading the segment registers.
To generate a diff of this commit:
cvs rdiff -u -r1.250 -r1.251 src/sys/arch/i386/i386/trap.c
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/i386/i386/vector.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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