CVS commit: [matt-nb5-mips64] src/sys/arch/mips/rmi

[Cliff Neighbors <cliff%netbsd.org@localhost>]

Module Name:    src
Committed By:   cliff
Date:           Fri May 21 23:35:42 UTC 2010

Modified Files:
        src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c rmixl_intr.h

Log Message:
- rename IRT based interrupts to "pic int ..."
- rename rmixl_vecnames_common to "vec ..."
- move ipl_eimr_map table print into rmixl_ipl_eimr_map_print()
- consolidate debug print funcs at the end of the file
- 'irq' -- being somewhat ambiguous -- renamed to 'irt' throughout
  to reflect use as IRT index
- IRT-based interrupts are moved to EIRR/EIMR vectors (bits) 32..63
  to avoid all opverlap with EIRR/EIMR bits 0..7 which are CAUSE[8..15].
  To date this has been a non-issue since we aren't using the
  watchdog or timers there.  non-IRT interrupts (FMN and IPI) are moved
  to unused portion vectors 8, 9
- in rmixl_intr_init_cpu, instead of writing 0 to EIRR, ack with bits read
  (excluding CAUSE[8..15] bits) as defense against possible stale
  interrupts inherited from firmware (paranoid -- we aren't seeing any).
- rmixl_irt_establish gets a 'vec' arg for use in IRTENTRYC1 reg
  (no longer assume vec = irt)
- set/clear irq bits in ipl_eimr_map[] during interrupt establish/disestablish
- in evbmips_iointr(), mask off ints enabled at higher ipl; we only
  dispatch interrupts at highest enabling ipl.


To generate a diff of this commit:
cvs rdiff -u -r1.1.2.19 -r1.1.2.20 src/sys/arch/mips/rmi/rmixl_intr.c
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/rmi/rmixl_intr.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.