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CVS commit: src/sys/arch/arm/cortex



Module Name:    src
Committed By:   matt
Date:           Sun Mar 30 15:20:54 UTC 2014

Modified Files:
        src/sys/arch/arm/cortex: a9_mpsubr.S

Log Message:
Improve MP startup code.  We now use a two stage startup, after creating
the initial L1PT and turning on the MMU/caches, we spinup the secondary CPUs
waiting for them to get the same state as the boot processor.  Once the
real L1PT is initialized and used, the secondary CPUs are kicked so they can
use it (and the initial L1PT is discarded).  Finally, wait until NetBSD
kicks the secondary CPUs then load the stack from the idlelwp and then hatch
the cpu and then jump to idle_loop.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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