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CVS commit: src/sys/arch/mips/ralink



Module Name:    src
Committed By:   matt
Date:           Wed Apr 30 00:52:49 UTC 2014

Modified Files:
        src/sys/arch/mips/ralink: ralink_mainbus.c

Log Message:
Instead of
mainbus0 (root): Ralink System Bus
be more explicit about the system:
mainbus0 (root): Mediatek MT7620 System Bus


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ralink/ralink_mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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