CVS commit: [netbsd-7] src

["Martin Husemann" <martin%netbsd.org@localhost>]

Module Name:    src
Committed By:   martin
Date:           Sun Mar  6 17:49:56 UTC 2016

Modified Files:
        src/sys/arch/x86/include [netbsd-7]: cacheinfo.h specialreg.h
        src/usr.sbin/cpuctl/arch [netbsd-7]: i386.c

Log Message:
Pull up the following changes, requested by msaitoh in #1117:

        sys/arch/x86/include/cacheinfo.h                1.20-1.21
        sys/arch/x86/include/specialreg.h               1.83-1.86
        usr.sbin/cpuctl/arch/i386.c                     1.67-1.70

Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
  Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
  for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"


To generate a diff of this commit:
cvs rdiff -u -r1.18.2.1 -r1.18.2.2 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.78.4.3 -r1.78.4.4 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.58.2.4 -r1.58.2.5 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.