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CVS commit: src/sys/arch/mips/mips



Module Name:    src
Committed By:   skrll
Date:           Sun Aug  7 07:13:57 UTC 2016

Modified Files:
        src/sys/arch/mips/mips: mipsX_subr.S

Log Message:
Fix two bugs for tlb_invalidate_addr for (PGSHIFT & 1) == 0

- t0/t1 weren't being updated when both lo0/lo1 become invalid
- the global bit (G) needs to be preserved if the entry becomes invalid

The MIPSNN optimisation is disabled for now as it needs to be updated
appropriately


To generate a diff of this commit:
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/mips/mips/mipsX_subr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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