CVS commit: src/sys/arch/mips/mips

["Michael Lorenz" <macallan%netbsd.org@localhost>]

Module Name:    src
Committed By:   macallan
Date:           Fri Nov 18 13:50:36 UTC 2016

Modified Files:
        src/sys/arch/mips/mips: spl.S

Log Message:
don't blindly zero STATUS in order to disable interrupts, instead take care
to preserve bits like KX in case we catch an interrupt between mtc0 and the
write actually taking effect
now n32 kernels on my O2 are (mostly) stable again
ok skrll@


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/mips/spl.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.